ADC1112D125F2/DB,598 NXP Semiconductors, ADC1112D125F2/DB,598 Datasheet - Page 24

• Manufacturer Part Number: ADC1112D125F2/DB,598
• Description: BOARD EVALUATION FOR ADC1112D125
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of ADC1112D125F2/DB,598

• Design Resources: ADC1x12D Demo Brd PCB Files
• Number Of Adc's: 2
• Number Of Bits: 11
• Sampling Rate (per Second): 125M
• Data Interface: Serial, LVDS/DDR
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 1.23W @ 125MSPS
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC1112D125
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6891

NXP Semiconductors
ADC1112D125
Product data sheet
11.4.3 Duty cycle stabilizer
11.4.4 Clock input divider
11.5.1 Digital output buffers: CMOS mode
11.5 Digital outputs
Single-ended or differential clock inputs can be selected via the SPI interface
(see
control bit SE_SEL.
If single-ended is implemented without setting bit SE_SEL to the appropriate value, the
unused pin should be connected to ground via a capacitor.
The duty cycle stabilizer can improve the overall performance of the ADC by
compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is
active (bit DCS_EN = logic 1; see
of between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled
(DCS_EN = logic 0), the input clock signal should have a duty cycle of between 45 % and
55 %.
The ADC1112D125 contains an input clock divider that divides the incoming clock by a
factor of 2 (when bit CLKDIV = logic 1; see
deliver a higher clock frequency with better jitter performance, leading to a better SNR
result once acquisition has been performed.
The digital output buffers can be configured as CMOS by setting bit LVDS_CMOS to
logic 0 (see
Each digital output has a dedicated output buffer. The equivalent circuit of the CMOS
digital output buffer is shown in
AGND/V
Each buffer can be loaded by a maximum of 10 pF.
Fig 29. CMOS digital output buffer
Table
DDO
22). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via
Table
to ensure 1.8 V to 3.3 V compatibility and is isolated from the ADC core.
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DRIVER
24).
LOGIC
Rev. 2 — 3 March 2011
Figure
Dual 11-bit ADC: CMOS or LVDS DDR digital outputs
Table
50 Ω
29. The buffer is powered by a separate
22), the circuit can handle signals with duty cycles
Parasitics
Table
22). This feature allows the user to
ESD
ADC1112D125
Package
005aaa057
© NXP B.V. 2011. All rights reserved.
VDDO
Dx
AGND
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