ADC1112D125F2/DB,598 NXP Semiconductors, ADC1112D125F2/DB,598 Datasheet - Page 25

• Manufacturer Part Number: ADC1112D125F2/DB,598
• Description: BOARD EVALUATION FOR ADC1112D125
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of ADC1112D125F2/DB,598

• Design Resources: ADC1x12D Demo Brd PCB Files
• Number Of Adc's: 2
• Number Of Bits: 11
• Sampling Rate (per Second): 125M
• Data Interface: Serial, LVDS/DDR
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 1.23W @ 125MSPS
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC1112D125
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6891

NXP Semiconductors
ADC1112D125
Product data sheet
11.5.2 Digital output buffers: LVDS DDR mode
The output resistance is 50 Ω and is the combination of an internal resistor and the
equivalent output resistance of the buffer. There is no need for an external damping
resistor. The drive strength of both DATA and DAV buffers can be programmed via the SPI
in order to adjust the rise and fall times of the output digital signals (see
The digital output buffers can be configured as LVDS DDR by setting bit LVDS_CMOS to
logic 1 (see
Each output should be terminated externally with a 100 Ω resistor (typical) at the receiver
side
(see
The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via
the SPI (bits DAVI[1:0] and DATAI[1:0]; see
voltage levels.
Fig 30. LVDS DDR digital output buffer - externally terminated
Fig 31. LVDS DDR digital output buffer - internally terminated
(Figure
Figure 31
+
-
+
Table
-
30) or internally via SPI control bits LVDS_INT_TER[2:0]
and
All information provided in this document is subject to legal disclaimers.
24).
Table
3.5 mA
typical
3.5 mA
typical
Rev. 2 — 3 March 2011
33).
+
100 Ω
-
+
-
VDDO
DAn_DAn + 1_P; DBn_DBn + 1_P
DAn_DAn + 1_M; DBn_DBn + 1_M
AGND
Dual 11-bit ADC: CMOS or LVDS DDR digital outputs
VDDO
DAn_DAn + 1_P; DBn_DBn + 1_P
DAn_DAn + 1_M; DBn_DBn + 1_M
AGND
Table
32) in order to adjust the output logic
ADC1112D125
100 Ω
100 Ω
005aaa112
005aaa113
RECEIVER
© NXP B.V. 2011. All rights reserved.
RECEIVER
Table
31).
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