ADC1112D125F2/DB,598 NXP Semiconductors, ADC1112D125F2/DB,598 Datasheet - Page 17

• Manufacturer Part Number: ADC1112D125F2/DB,598
• Description: BOARD EVALUATION FOR ADC1112D125
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of ADC1112D125F2/DB,598

• Design Resources: ADC1x12D Demo Brd PCB Files
• Number Of Adc's: 2
• Number Of Bits: 11
• Sampling Rate (per Second): 125M
• Data Interface: Serial, LVDS/DDR
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 1.23W @ 125MSPS
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC1112D125
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6891

NXP Semiconductors
ADC1112D125
Product data sheet
11.1.4
11.2.1 Input stage
11.2.2 Anti-kickback circuitry
11.2 Analog inputs
Selecting the output data format
The output data format can be selected via the SPI interface (offset binary, two’s
complement or gray code; see
binary or two’s complement). Offset binary is selected when DFS is LOW. When DFS is
HIGH, two’s complement is selected.
The analog input of the ADC1112D125 supports a differential or a single-ended input
drive. Optimal performance is achieved using differential inputs with the common-mode
input voltage (V
The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
via a programmable internal reference (see
The equivalent circuit of the sample-and-hold input stage, including ElectroStatic
Discharge (ESD) protection and circuit and package parasitics, is shown in
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
Anti-kickback circuitry (RC filter in
injection generated by the sampling capacitance.
The RC-filter is also used to filter noise from the signal before it reaches the sampling
stage. The value of the capacitor should be chosen to maximize noise attenuation without
degrading the settling time excessively.
Fig 16. Input sampling circuit
INAM/INBM
INAP/INBP
All information provided in this document is subject to legal disclaimers.
I(cm)
) on pins INAP, INAM, INBP and INBM set to 0.5V
Rev. 2 — 3 March 2011
Package
Table
Dual 11-bit ADC: CMOS or LVDS DDR digital outputs
Figure 17
24) or by using pin DFS in Pin control mode (offset
ESD
Section 11.3
is needed to counteract the effects of charge
Parasitics
and
R on = 14 Ω
R on = 14 Ω
internal
internal
Switch
Switch
clock
clock
ADC1112D125
Table
Sampling
Sampling
capacitor
capacitor
23).
4 pF
4 pF
DDA
© NXP B.V. 2011. All rights reserved.
005aaa092
.
Figure
16.
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