ADC1112D125F2/DB,598 NXP Semiconductors, ADC1112D125F2/DB,598 Datasheet - Page 32

• Manufacturer Part Number: ADC1112D125F2/DB,598
• Description: BOARD EVALUATION FOR ADC1112D125
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of ADC1112D125F2/DB,598

• Design Resources: ADC1x12D Demo Brd PCB Files
• Number Of Adc's: 2
• Number Of Bits: 11
• Sampling Rate (per Second): 125M
• Data Interface: Serial, LVDS/DDR
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 1.23W @ 125MSPS
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC1112D125
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6891

NXP Semiconductors
Table 23.
Default values are highlighted.
Table 24.
Default values are highlighted.
ADC1112D125
Product data sheet
Bit
7 to 4
3
2 to 0
Bit
7 to 5
4
3
2
1 to 0
Symbol
-
INTREF_EN
INTREF[2:0]
Symbol
-
LVDS_CMOS
OUTBUF
OUTBUS_SWAP
DATA_FORMAT[1:0]
Internal reference control register (address 0008h) bit description
Output data standard control register (address 0011h) bit description
All information provided in this document is subject to legal disclaimers.
Access
-
R/W
R/W
Access
-
R/W
R/W
R/W
R/W
Rev. 2 — 3 March 2011
Value
0000
0
1
000
001
010
011
100
101
110
111
Value
000
0
1
0
1
0
1
00
01
10
11
Dual 11-bit ADC: CMOS or LVDS DDR digital outputs
Description
not used
programmable internal reference enable
programmable internal reference
Description
not used
output data standard: LVDS DDR or CMOS
output data format
output buffers enable
output bus swap
disabled
active
0 dB (FS = 2 V)
−1 dB (FS = 1.78 V)
−2 dB (FS = 1.59 V)
−3 dB (FS = 1.42 V)
−4 dB (FS = 1.26 V)
−5 dB (FS = 1.12 V)
−6 dB (FS = 1 V)
reserved
CMOS
LVDS DDR
output enabled
output disabled (high-Z)
no swapping
output bus is swapped (MSB becomes LSB and
vice versa)
offset binary
two’s complement
gray code
offset binary
ADC1112D125
© NXP B.V. 2011. All rights reserved.
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