ADC1112D125F2/DB,598 NXP Semiconductors, ADC1112D125F2/DB,598 Datasheet - Page 6

• Manufacturer Part Number: ADC1112D125F2/DB,598
• Description: BOARD EVALUATION FOR ADC1112D125
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of ADC1112D125F2/DB,598

• Design Resources: ADC1x12D Demo Brd PCB Files
• Number Of Adc's: 2
• Number Of Bits: 11
• Sampling Rate (per Second): 125M
• Data Interface: Serial, LVDS/DDR
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 1.23W @ 125MSPS
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC1112D125
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6891

NXP Semiconductors
ADC1112D125
Product data sheet
6.2.2 Pin description
Table 3.
[1]
[2]
Symbol
DB9_DB10_M
DB9_DB10_P
DB7_DB8_M
DB7_DB8_P
DB5_DB6_M
DB5_DB6_P
DB3_DB4_M
DB3_DB4_P
DB1_DB2_M
DB1_DB2_P
LOW_DB0_M
LOW_DB0_P
n.c.
n.c.
DAVM
DAVP
n.c.
n.c.
LOW_DA0_P
LOW_DA0_M
DA1_DA2_P
DA1_DA2_M
DA3_DA4_P
DA3_DA4_M
DA5_DA6_P
DA5_DA6_M
DA7_DA8_P
DA7_DA8_M
DA9_DA10_P
DA9_DA10_M
Pins 1 to 24, pin 59 to 64 and pins 31, 32, 49 and 50 are the same for both CMOS and LVDS DDR outputs
(see
P: power supply; G: ground; I: input; O: output; I/O: input/output.
Table
Pin description (LVDS DDR) digital outputs)
2).
All information provided in this document is subject to legal disclaimers.
25
27
28
29
30
33
34
35
36
37
38
39
40
43
44
45
46
47
48
51
52
53
54
55
56
58
Pin
26
41
42
57
Type
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Rev. 2 — 3 March 2011
[2]
Description
differential output data DB9 and DB10 multiplexed, complement
differential output data DB9 and DB10 multiplexed, true
differential output data DB7and DB8 multiplexed, complement
differential output data DB7 and DB8 multiplexed, true
differential output data DB5 and DB6 multiplexed, complement
differential output data DB5 and DB6 multiplexed, true
differential output data DB3 and DB4 multiplexed, complement
differential output data DB3 and DB4 multiplexed, true
differential output data DB1 and DB2 multiplexed, complement
differential output data DB1 and DB2 multiplexed, true
differential output data DB0 multiplexed, complement
differential output data DB0 multiplexed, true
not connected
not connected
data valid output clock, complement
data valid output clock, true
not connected
not connected
differential output data DA0 multiplexed, true
differential output data DA0 multiplexed, complement
differential output data DA1 and DA2 multiplexed, true
differential output data DA1 and DA2 multiplexed, complement
differential output data DA3 and DA4 multiplexed, true
differential output data DA3 and DA4 multiplexed, complement
differential output data DA5 and DA6 multiplexed, true
differential output data DA5 and DA6 multiplexed, complement
differential output data DA7 and DA8 multiplexed, true
differential output data DA7 and DA8 multiplexed, complement
differential output data DA9 and DA10 multiplexed, true
differential output data DA9 and DA10 multiplexed, complement
Dual 11-bit ADC: CMOS or LVDS DDR digital outputs
[1]
ADC1112D125
© NXP B.V. 2011. All rights reserved.
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