ADC1112D125F2/DB,598 NXP Semiconductors, ADC1112D125F2/DB,598 Datasheet - Page 16

• Manufacturer Part Number: ADC1112D125F2/DB,598
• Description: BOARD EVALUATION FOR ADC1112D125
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of ADC1112D125F2/DB,598

• Design Resources: ADC1x12D Demo Brd PCB Files
• Number Of Adc's: 2
• Number Of Bits: 11
• Sampling Rate (per Second): 125M
• Data Interface: Serial, LVDS/DDR
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 1.23W @ 125MSPS
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC1112D125
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6891

NXP Semiconductors
11. Application information
ADC1112D125
Product data sheet
11.1.1 SPI and Pin control modes
11.1.2 Operating mode selection
11.1.3
11.1 Device control
The ADC1112D125 can be controlled via the Serial Peripheral Interface (SPI control
mode) or directly via the I/O pins (Pin control mode).
The device enters Pin control mode at power-up and remains in this mode as long as pin
CS is held HIGH. In Pin control mode, the SPI pins SDIO, CS and SCLK are used as
static control pins.
SPI control mode is enabled by forcing pin CS LOW. Once SPI control mode has been
enabled, the device remains in this mode. The transition from Pin control mode to SPI
control mode is illustrated in
When the device enters SPI control mode, the output data standard and data format are
determined by the level on pin SDIO as soon as a transition is triggered by a falling edge
on CS.
The active ADC1112D125 operating mode (Power-up, Power-down or Sleep) can be
selected via the SPI interface (see
Table 10.
Selecting the output data standard
The output data standard (CMOS or LVDS DDR) can be selected via the SPI interface
(see
ODS is HIGH, otherwise CMOS is selected.
Pin CTRL
0
0.3V
0.6V
V
Fig 15. Control mode selection
DDA
DDA
DDA
Table
Operating mode selection via pin CTRL
24) or by using pin ODS in Pin control mode. LVDS DDR is selected when
SCLK/DFS
SDIO/ODS
All information provided in this document is subject to legal disclaimers.
CS
Rev. 2 — 3 March 2011
two's complement
Pin control mode
Data format
LVDS DDR
Figure
Operating mode
Power-down
Sleep
Power-up
Power-up
Dual 11-bit ADC: CMOS or LVDS DDR digital outputs
Table
15.
21) or by using pin CTRL in Pin control mode.
offset binary
Data format
CMOS
R/W
SPI control mode
ADC1112D125
W1
Output high-Z
yes
yes
yes
no
W0
005aaa039
A12
© NXP B.V. 2011. All rights reserved.
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