ADC1112D125F2/DB,598 NXP Semiconductors, ADC1112D125F2/DB,598 Datasheet - Page 33

• Manufacturer Part Number: ADC1112D125F2/DB,598
• Description: BOARD EVALUATION FOR ADC1112D125
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of ADC1112D125F2/DB,598

• Design Resources: ADC1x12D Demo Brd PCB Files
• Number Of Adc's: 2
• Number Of Bits: 11
• Sampling Rate (per Second): 125M
• Data Interface: Serial, LVDS/DDR
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 1.23W @ 125MSPS
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC1112D125
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6891

NXP Semiconductors
Table 25.
Default values are highlighted.
[1]
Table 26.
Default values are highlighted.
Table 27.
Default values are highlighted.
ADC1112D125
Product data sheet
Bit
7 to 4
3
2 to 0
Bit
7 to 6
5 to 0
Bit
7 to 3
2 to 0
t
clk
= 1 / f
Symbol
-
DAVINV
DAVPHASE[2:0]
Symbol
-
DIG_OFFSET[5:0]
Symbol
-
TESTPAT_SEL[2:0]
Output clock register (address 0012h) bit description
Offset register (address 0013h) bit description
Test pattern 1 register (address 0014h) bit description
clk
All information provided in this document is subject to legal disclaimers.
Access
-
R/W
R/W
Access
-
R/W
Access
-
R/W
Rev. 2 — 3 March 2011
Value
0000
0
1
000
001
010
011
100
101
110
111
Value
00
011111
...
000000
...
100000
Value
00000
000
001
010
011
100
101
110
111
Dual 11-bit ADC: CMOS or LVDS DDR digital outputs
Description
not used
output clock data valid (DAV) polarity
DAV phase select
Description
not used
Description
not used
digital test pattern select
digital offset adjustment
mid scale
normal
inverted
output clock shifted (ahead) by 6/16 × t
output clock shifted (ahead) by 5/16 × t
output clock shifted (ahead) by 4/16 × t
output clock shifted (ahead) by 3/16 × t
output clock shifted (ahead) by 2/16 × t
output clock shifted (ahead) by 1/16 × t
default value as defined in timing section
output clock shifted (delayed) by 1/16 × t
+31 LSB
...
0
...
−32 LSB
off
−FS
+FS
toggle ‘1111..1111’/’0000..0000’
custom test pattern
‘0101..0101’
‘1010..1010.’
ADC1112D125
© NXP B.V. 2011. All rights reserved.
clk
clk
clk
clk
clk
clk
clk
[1]
[1]
[1]
[1]
[1]
[1]
[1]
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