ADC1112D125F2/DB,598 NXP Semiconductors, ADC1112D125F2/DB,598 Datasheet - Page 27

• Manufacturer Part Number: ADC1112D125F2/DB,598
• Description: BOARD EVALUATION FOR ADC1112D125
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of ADC1112D125F2/DB,598

• Design Resources: ADC1x12D Demo Brd PCB Files
• Number Of Adc's: 2
• Number Of Bits: 11
• Sampling Rate (per Second): 125M
• Data Interface: Serial, LVDS/DDR
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 1.23W @ 125MSPS
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC1112D125
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6891

NXP Semiconductors
ADC1112D125
Product data sheet
11.5.6 Test patterns
11.5.7 Output codes versus input voltage
11.6.1 Register description
11.6 Serial Peripheral Interface (SPI)
For test purposes, the ADC1112D125 can be configured to transmit one of a number of
predefined test patterns (via bits TESTPAT_SEL[2:0]; see
can be defined by the user (TESTPAT_USER[10:3]; see
TESTPAT_USER[2:0]; see
The selected test pattern is transmitted regardless of the analog input.
Table 16.
The ADC1112D125 serial interface is a synchronous serial communications port that
allows easy interfacing with many commonly used microprocessors. It provides access to
the registers that control the operation of the chip.
This interface is configured as a 3-wire type (SDIO as bidirectional pin)
Pin SCLK is the serial clock input and pin CS acts as the serial chip select.
Each read/write operation is initiated by a LOW level on CS. A minimum of three bytes is
transmitted (two instruction bytes and at least one data byte). The number of data bytes is
determined by the value of bits W1 and W2 (see
V
< −1
−1.0000000
−0.9990234
−0.9980469
−0.9970703
−0.996093
....
−0.0019531
−0.0009766
0.0000000
+0.0009766
+0.0019531
....
+0.9960938
+0.9970703
+0.9980469
+0.9990234
+1.0000000
> +1
INAP
− V
INAM
Output codes
/V
INBP
All information provided in this document is subject to legal disclaimers.
− V
INBM
Rev. 2 — 3 March 2011
Table
Offset binary
000 0000 0000
000 0000 0000
000 0000 0001
000 0000 0010
000 0000 0011
000 0000 0100
....
011 1111 1110
011 1111 1111
100 0000 0000
100 0000 0001
100 0000 0010
....
111 1111 1011
111 1111 1100
111 1111 1101
111 1111 1110
111 1111 1111
111 1111 1111
Dual 11-bit ADC: CMOS or LVDS DDR digital outputs
29) and is selected when TESTPAT_SEL[2:0] = 101.
Table
Two’s complement
100 0000 0000
100 0000 0000
100 0000 0001
100 0000 0010
100 0000 0011
100 0000 0100
....
111 1111 1110
111 1111 1111
000 0000 0000
000 0000 0001
000 0000 0010
....
011 1111 1011
011 1111 1100
011 1111 1101
011 1111 1110
011 1111 1111
011 1111 1111
18).
Table 28
Table
ADC1112D125
27). A custom test pattern
and
© NXP B.V. 2011. All rights reserved.
OTRA/OTRB pin
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
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