ADC1112D125F2/DB,598 NXP Semiconductors, ADC1112D125F2/DB,598 Datasheet - Page 8

• Manufacturer Part Number: ADC1112D125F2/DB,598
• Description: BOARD EVALUATION FOR ADC1112D125
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of ADC1112D125F2/DB,598

• Design Resources: ADC1x12D Demo Brd PCB Files
• Number Of Adc's: 2
• Number Of Bits: 11
• Sampling Rate (per Second): 125M
• Data Interface: Serial, LVDS/DDR
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 1.23W @ 125MSPS
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC1112D125
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6891

NXP Semiconductors
Table 6.
ADC1112D125
Product data sheet
Symbol
Clock inputs: pins CLKP and CLKM
Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
V
Sine
V
Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS)
V
V
Logic input: pin CTRL
V
V
I
I
Serial peripheral interface: pins CS, SDIO/ODS, SCLK/DFS
V
V
I
I
C
Digital outputs, CMOS mode: pins DA10 to DA0, DB10 to DB0, OTRA, OTRB and DAV
Output levels, V
V
V
C
Output levels, V
V
V
Digital outputs, LVDS DDR mode: pins DA9_DA10_P to LOW_DA0_P, DA9_DA10_M to LOW_DA0_M,
DB9_DB10_P to LOW_DB0_P, DB9_DB10_M to LOW_DB0_M, DAVP and DAVM
Output levels, V
V
V
C
Analog inputs: pins INAP, INAM, INBP and INBM
I
R
C
V
IL
IH
IL
IH
I
i(clk)dif
i(clk)dif
IL
IH
IL
IH
IL
IH
OL
OH
OL
OH
O(offset)
O(dif)
I(cm)
I
O
O
I
I
Static characteristics
DDO
DDO
DDO
Parameter
differential clock input voltage
differential clock input voltage
LOW-level input voltage
HIGH-level input voltage
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
LOW-level input voltage
HIGH-level input voltage
LOW-level input current
HIGH-level input current
input capacitance
LOW-level output voltage
HIGH-level output voltage
output capacitance
LOW-level output voltage
HIGH-level output voltage
output offset voltage
differential output voltage
output capacitance
input current
input resistance
input capacitance
common-mode input voltage
= 3 V
= 1.8 V
= 3 V only, R
L
[1]
= 100 Ω
…continued
All information provided in this document is subject to legal disclaimers.
Conditions
peak-to-peak
peak-to-peak
LOW-medium level
medium-HIGH level
high impedance; see
output buffer current set to
3.5 mA
output buffer current set to
3.5 mA
V
Rev. 2 — 3 March 2011
INAP
= V
INAM
Dual 11-bit ADC: CMOS or LVDS DDR digital outputs
; V
INBP
= V
Table 10
INBM
Min
-
±0.8
-
0.7V
-
-
-
-
−10
−10
0
0.7V
−10
−50
-
AGND
0.8V
-
AGND
0.8V
-
-
-
−5
-
-
0.9
DDA
DDA
DDO
DDO
ADC1112D125
Typ
±1.6
±3.0
-
-
0
0.3V
0.6V
V
-
-
-
-
-
-
4
-
-
3
-
-
1.2
350
3
-
19.8
2.8
1.5
DDA
DDA
DDA
© NXP B.V. 2011. All rights reserved.
Max
-
-
0.3V
-
-
-
-
-
+10
+10
0.3V
V
+10
+50
-
0.2V
V
-
0.2V
V
-
-
-
+5
-
-
2
DDA
DDO
DDO
DDA
DDA
DDO
DDO
Unit
V
V
V
V
V
V
V
V
μA
μA
V
V
μA
μA
pF
V
V
pF
V
V
V
mV
pF
μA
kΩ
pF
V
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