MC68EC040RC25 Freescale Semiconductor, MC68EC040RC25 Datasheet - Page 101

• Manufacturer Part Number: MC68EC040RC25
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC040RC25

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 179
• Package Type: PGA
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NOTE: Dirty state transitions D4 and D6 are the result of a system programming error and should be avoided even
MOTOROLA
CPU Read Miss
CPU Read Hit
CPU Write Miss
(Copyback)
CPU Write Miss
(Write-through)
CPU Write Hit
(Copyback)
CPU Write Hit
(Write-through)
Cache Invalidate
(CINV)
Cache Push
(CPUSH)
Alternate Master Read Hit
(Snoop Control = 01
— Leave Dirty)
Cache Operation
though they are technically valid.
Table 4-4. Data-Cache Line State Transitions
I3
I4
I5
I6
I7
I8
I9
I1
I2
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memory; supply data
to CPU and update
cache; go to valid
state.
Read line from
memory into cache;
write data to cache;
set Dn bits of modified
long words; go to dirty
state.
Write data to memory;
remain in current state.
Not Possible
Not Possible
No action; remain in
current state.
No action; remain in
current state.
Not Possible
Read line from
Not Possible
Invalid Cases
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M68040 USER’S MANUAL
V1 Read line from
V3 Read line from
V4 Write data to memory;
V7 No action; go to invalid
V8 No action; go to invalid
V2 Supply data to CPU;
V5 Write data into cache;
V6 Write data to cache;
V9 No action; remain in
Current State
memory; supply data
to CPU and update
cache (replacing old
line); remain in current
state.
remain in current state.
memory into cache
(replacing old line);
write data to cache
and set Dn bits; go to
dirty state.
remain in current state.
set Dn bits of modified
long words; go to dirty
state.
write data to memory;
remain in current state.
state.
state.
current state.
Valid Cases
D1 Buffer dirty cache line;
D2 Supply data to CPU;
D3 Buffer dirty cache line;
D4 Write data to memory;
D5 Write data in cache;
D6 Write data into cache
D7 No action (dirty data
D8 Write dirty data to
D9 Inhibit memory and
read new line from
memory; supply data
to CPU and update
cache; write buffered
dirty data to memory;
go to valid state.
remain in current state.
read new line from
memory; write data to
cache and set Dn bits;
write buffered dirty
data to memory;
remain in current state.
remain in current state
(see note).
set Dn bits of modified
long words; remain in
current state.
(no change to Dn bits);
write data to memory;
remain in current state
(see note).
lost); go to invalid
state.
memory; go to invalid
state.
source data; remain in
current state.
Dirty Cases
4- 17