MC68EC040RC25 Freescale Semiconductor, MC68EC040RC25 Datasheet - Page 306

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MC68EC040RC25

Manufacturer Part Number
MC68EC040RC25
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68EC040RC25

Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
179
Package Type
PGA
Lead Free Status / Rohs Status
Supplier Unconfirmed

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10.6 INTEGER UNIT INSTRUCTION TIMINGS (Continued)
MOTOROLA
NOTES:
Dn
An
(An)
(An)+
–(An)
(d 16 ,An)
(d 16 ,PC)
(xxx).W, (xxx).L
#<xxx>
(d 8 ,An,Xn)
(d 8 ,PC,Xn)
(BR,Xn)
(bd,BR,Xn)
([bd,BR,Xn])
([bd,BR,Xn],od)
([bd,BR],Xn)
([bd,BR],Xn,od)
a. Bit instruction <ea> calculate and execute times T1/T2 apply to #<xxx>/Dn bit numbers.
b. This instruction interlocks the <ea> calculate and execute stages.
c. If the bit field spans a long-word boundary, add ten and nine clocks to the <ea> calculate and execute times,
d. If the bit field spans a long-word boundary, add two clocks to the execute time. Two memory addresses are
e. Immediate count specified for both width and offset and width and/or offset specified in register, respectively.
Addressing
Mode
respectively. Two memory addresses are accessed in this case.
accessed in this case.
Calculate
<ea>
BCHG, BCLR, BSET a
2/1
2/1
11
12
10
11
1
1
1
1
3
7
8
Freescale Semiconductor, Inc.
For More Information On This Product,
1 L + 12/1 L + 13
3 L + 11/3 L + 12
1 L + 11/1 L + 12
3 L + 10/3 L + 11
1 L + 9/1 L + 10
1 L + 8/1 L + 9
Execute
1 L + 3/4
1 L + 3/4
3/4
3/4
3/4
3/4
5/6
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M68040 USER’S MANUAL
BFCHG, BFCLR, BFSET b,c
Calculate
<ea>
3/4 e
10
13
14
16
17
17
18
9
9
9
Execute
1 L + 13
1 L + 14
1 L + 16
1 L + 17
3 L + 15
3 L + 16
2 L + 8
2 L + 8
2 L + 8
6/7 e
11
Calculate
<ea>
BFEXTS, BFEXTU b,d
1/2 e
10
10
11
13
14
16
17
17
18
9
9
9
Execute
1 L + 10
1 L + 12
1 L + 13
1 L + 15
1 L + 16
3 L + 14
3 L + 15
2 L + 7
2 L + 7
3 L + 7
2 L + 7
4/5 e
10
10-15

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