MC68EC040RC25 Freescale Semiconductor, MC68EC040RC25 Datasheet - Page 159

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MC68EC040RC25

Manufacturer Part Number
MC68EC040RC25
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68EC040RC25

Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
179
Package Type
PGA
Lead Free Status / Rohs Status
Supplier Unconfirmed

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Clock 5 (C5)
MOTOROLA
This clock is identical to C3 except that once TA is recognized, the latched value
corresponds to the third long word of data for the burst. After the processor recognizes
the last TA assertion and terminates the line read bus cycle, TIP remains asserted if the
processor is ready to begin another bus cycle. Otherwise, the processor negates TIP
during the first half of the next clock.
Figures 7-12 and 7-13 illustrate a flowchart and functional timing diagram for a burst-
inhibited line read bus cycle.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
M68040 USER’S MANUAL
7- 17

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