MC68EC040RC25 Freescale Semiconductor, MC68EC040RC25 Datasheet - Page 166

• Manufacturer Part Number: MC68EC040RC25
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC040RC25

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 179
• Package Type: PGA
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Clock 1 (C1)
7-24
The line write cycle starts in C1. During the first half of C1, the processor places valid
values on the address bus and transfer attributes. For user and supervisor mode
accesses that are translated by the corresponding memory unit, UPAx signals are
driven with the values from the matching U1 and U0 bits. The TTx and TMx signals
identify the specific access type. The R/W signal is driven low for a write cycle, and
SIZ1 and SIZ0 indicate line size. CIOUT is asserted for a MOVE16 operand read if the
access is identified as noncachable. Refer to Section 3 Memory Management Unit
(Except MC68EC040 and MC68EC040V) for information on the M68040 and
UPA1, UPA0
NOTE: The selected device increments the value of A3 and A2.
SIZ1, SIZ0
TM2–TM0
TT1, TT0
D31–D0
A31–A4
CIOUT
A2–A0
BCLK
Figure 7-17. Line Write Transfer Timing
R/W
Freescale Semiconductor, Inc.
TIP
TS
TA
A3
For More Information On This Product,
A3, A2 =
C1
M68040 USER’S MANUAL
Go to: www.freescale.com
C2
01
C3
10
C4
11
C5
00
MOTOROLA