MC68EC040RC25 Freescale Semiconductor, MC68EC040RC25 Datasheet - Page 194

• Manufacturer Part Number: MC68EC040RC25
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC040RC25

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 179
• Package Type: PGA
• Lead Free Status / Rohs Status: Supplier Unconfirmed

7.8.2 Bus Arbitration Examples
The following paragraphs illustrate the behavior of the M68040 bus arbitration scheme
and provide examples of how an external bus arbiter can be designed to keep the integrity
of locked bus operations. The examples include the previously mentioned indeterminate
and disregard request conditions.
7.8.2.1 DUAL M68040 FAIRNESS ARBITRATION. The following state diagram illustrates
a fairness algorithm using two MC68040s and assigning the least priority to the processor
that owns the bus. If both processors keep their respective BR signals asserted, bus
ownership alternates between the two processors so that each processor can run at least
one bus cycle during its tenure. Each processor is allowed to own the bus without
relinquishing it to maintain the integrity of locked transfers. This example also illustrates
7-52
ATTRIBUTES
*
AM indicates the alternate bus master.
TRANSFER
AM_BG
AM_BR
D31–D0
A31–A0
BCLK
Figure 7-34. Implicit Bus Ownership Arbitration Timing
TIP
BR
BG
TA
BB
TS
*
*
Undefined
C1
ALTERNATE
MASTER
Freescale Semiconductor, Inc.
For More Information On This Product,
C2
M68040 USER’S MANUAL
Go to: www.freescale.com
C3
C4
IMPLICITLY
OWNED
BUS
C5
C6
BUS OWNED
AND ACTIVE
PROCESSOR
C7
C8
BUS OWNED
AND IDLE
C9
MOTOROLA