MC68EC040RC25 Freescale Semiconductor, MC68EC040RC25 Datasheet - Page 207

• Manufacturer Part Number: MC68EC040RC25
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC040RC25

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 179
• Package Type: PGA
• Lead Free Status / Rohs Status: Supplier Unconfirmed

7.10 RESET OPERATION
An external device asserts the reset input signal (RSTI) to reset the processor. When
power is applied to the system, external circuitry should assert RSTI for a minimum of 10
BCLK cycles after V
the power-on reset operation, illustrating the relationships among V
selects, and bus signals. The BCLK and PCLK clock signals are required to be stable by
the time V
MOTOROLA
CC
Figure 7-43. Snooped Long-Word Write, Memory Inhibited
reaches the minimum operating specification. The V
SIZ1, SIZ0
SC1, SC0
*
AM_BG
TT1, TT0
AM_BR
D31–D0
A31–A0
AM indicates the alternate bus master.
BCLK
R/W
BR
BG
TA
BB
TS
MI
*
*
CC
Freescale Semiconductor, Inc.
is within tolerance. Figure 7-44 is a functional timing diagram of
C1
For More Information On This Product,
C2
Go to: www.freescale.com
MEMORY INHIBITED FROM RESPONDING
M68040 USER’S MANUAL
ALTERNATE MASTER
LONG-WORD WRITE
C3
TA DRIVEN BY PROCESSOR
DATA WRITTEN BY ALTERNATE BUS MASTER
C4
C5
C6
IH
PROCESSOR
levels of the clocks
CC
, RSTI, mode
7- 65