MC68EC040RC25 Freescale Semiconductor, MC68EC040RC25 Datasheet - Page 289

• Manufacturer Part Number: MC68EC040RC25
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC040RC25

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 179
• Package Type: PGA
• Lead Free Status / Rohs Status: Supplier Unconfirmed

MOTOROLA
CMDREG1B
ETEMP
STAG
E1
T
CMDREG1B
ETEMP
STAG
FPTEMP
DTAG
E1
T
CMDREG1B
ETEMP
STAG
WBTEMP
E1
T
CMDREG1B
FPTEMP
STAG
E1
T
CMDREG3B
WBTEMP
WBTE15
E3
T
FSAVE State
Frame Field
Table 9-16. State Frame Field Information (Continued)
FMOVE Instruction Command Word
Unrounded Source Operand from Floating-Point Register, with SNAN bit set.
Source Operand Tag, indicated NAN.
Always 1
Always 1
Exception Instruction Command Word
Source operand is converted to extended precision.
Source Operand Tag
Destination operand tag, if any.
Always 1
Always 0
FMOVE Instruction Command Word
Unrounded Source Operand from Floating-Point Register
Source Operand Tag
Always 1
Always 1
Exception Instruction Command Word
Source Operand Tag = Normalized
Always 1
Always 0
Encoded Exception Instruction Command Word
to the correct precision.
Bit 15 of the intermediate result's 16-bit exponent = 0 for overflow.
Always 1
Either 1 or 0
Destination operand, if any, is converted to extended precision.
Contains the rounded integer used to check for erroneous integer overflow.
Intermediate result with mantissa rounded to correct precision.
WBTS, WBTE, and WBTM equal the intermediate result with mantissa rounded
Freescale Semiconductor, Inc.
For More Information On This Product,
OVFL (FADD, FSUB, FMUL, FDIV, and FSQRT)
OVFL (FMOVE to Register, FABS, and FNEG)
OPERR (For Opclass 000 and 010)
Go to: www.freescale.com
M68040 USER’S MANUAL
OPERR (For Opclass 011)
SNAN (For Opclass 011)
Contents
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