MC68EC040RC25 Freescale Semiconductor, MC68EC040RC25 Datasheet - Page 298

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MC68EC040RC25

Manufacturer Part Number
MC68EC040RC25
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68EC040RC25

Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
179
Package Type
PGA
Lead Free Status / Rohs Status
Supplier Unconfirmed

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Instructions using the brief and full extension word format addressing modes cause the
<ea> calculate and execute stages to operate in an interlocked manner. When these
instructions wait to begin execution in the execution stage, there is a similar increase in
the <ea> calculate time. Figure 10-3 illustrates this effect for an ADD instruction using a
brief format extension word. The ADD instruction stalls for two clocks waiting to enter the
execution stage. Since this time exceeds by one clock the ADD lead time, the ADD
instruction remains in the <ea> calculate stage for one additional clock. If the ADD
instruction was in the execution stage for two clocks, the ABCD instruction would not have
stalled in the <ea> calculate stage.
MOTOROLA
<ea> CALCULATE
NOTE: *Possible stalls in this stage.
WRITE-BACK
<ea> FETCH
EXECUTE
Freescale Semiconductor, Inc.
LABEL
For More Information On This Product,
P1
N1
N2
C1
P1
A
B
Figure 10-3. Interlocked Stages
C2
P1
A
Go to: www.freescale.com
M68040 USER’S MANUAL
TRAPF
ABCD
ADD.L
TRAPF
TRAPF
INSTRUCTION
C3
P1
B
A
D0,D1
4(A0,D3),D2
C4
B
B
A
C5
B
B
A
CALCULATE
C6
B*
B
A
<ea>
1
3
5
1
1
C7
B
B
B
C8
EXECUTE
B
B
B
1 L + 4
1
3
1
1
C9
N1
B
B
C10
N2
N1
B
C11
N2
N1
C12
N2
10-7

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