MC68EC040RC25 Freescale Semiconductor, MC68EC040RC25 Datasheet - Page 88

• Manufacturer Part Number: MC68EC040RC25
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC040RC25

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 179
• Package Type: PGA
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Both caches contain circuitry to automatically determine which cache line in a set to use
for a new line. The cache controller locates the first invalid line and uses it; if no invalid
lines exist, then a pseudo-random replacement algorithm is used to select a valid line,
replacing it with the new line. Each cache contains a 2-bit counter, which is incremented
for each access to the cache. The instruction cache counter is incremented for each half-
line accessed in the instruction cache. The data cache counter is incremented for each
half-line accessed during reads, for each full line accessed during writes in copyback
mode, and for each bus transfer resulting from a write in write-through mode. When a
miss occurs and all four lines in the set are valid, the line pointed to by the current counter
value is replaced, after which the counter is incremented.
4-4
SUPERVISOR
BIT
S
TRANSLATION
31
ADDRESS
CACHE
LA31–LA12
PAGE FRAME
PA31–PA12
LOGICAL ADDRESS
Freescale Semiconductor, Inc.
PA11–PA10
For More Information On This Product,
Figure 4-3. Caching Operation
TRANSLATED
PA31–PA10
PHYSICAL
ADDRESS
M68040 USER'S MANUAL
Go to: www.freescale.com
12
SET SELECT
PHYSICAL
PA9–PA4
SET 63
SET 0
SET 1
PAGE OFFSET
COMPARATOR
TAG
TAG
0
0
STATUS
STATUS
1
LINE 0
2
D0
D0
LINE 1
3
D1
D1
LINE 2
HIT 3
HIT 2
HIT 1
HIT 0
LINE 3
D2
D2
D3
D3
LOGICAL OR
MUX
LINE SELECT
MOTOROLA
INSTRUCTION
HIT
DATA OR