MC68EC040RC25 Freescale Semiconductor, MC68EC040RC25 Datasheet - Page 183

• Manufacturer Part Number: MC68EC040RC25
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC040RC25

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 179
• Package Type: PGA
• Lead Free Status / Rohs Status: Supplier Unconfirmed

7.6.2 Retry Operation
When an external device asserts both the TA and TEA signals during a bus cycle, the
processor enters the retry sequence. The processor terminates the bus cycle and
immediately retries the cycle using the same access information (address and transfer
attributes). However, if the bus cycle was a cache push operation, the bus is arbitrated
away from the M68040 before the retry operation, and a snoop during the arbitration
invalidates the cache push, then the processor does not use the same access information.
Figure 7-28 illustrates a functional timing diagram for a retry of a read bus transfer.
The processor retries any read or write cycles of a read-modify-write transfer separately;
LOCK remains asserted during the entire retry sequence. If the last bus cycle of a locked
access is retried, LOCKE remains asserted through the retry of the write cycle.
MOTOROLA
UPA1, UPA0
SIZ1, SIZ0
TM2–TM0
TT1, TT0
Figure 7-28. Retry Read Transfer Timing
Freescale Semiconductor, Inc.
A31–A0
D31–D0
CIOUT
BCLK
TIP
TEA
For More Information On This Product,
R/W
TS
TA
C1
Go to: www.freescale.com
M68040 USER’S MANUAL
RETRY SIGNALED
LONG WORD
READ CYCLE
C2
CW
C1
RETRY
CYCLE
C2
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