MC68EC040RC25 Freescale Semiconductor, MC68EC040RC25 Datasheet - Page 436

• Manufacturer Part Number: MC68EC040RC25
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC040RC25

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 179
• Package Type: PGA
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Access Control Unit, 1-2, B-4, B-5
Access Control Unit Register, B-5;
Access Error, 1-5, 3-22, 3-23, 3-24, 5-14, 7-37,
Access Fault, 3-9, 8-6, 8-7
Access Serialization, 7-44
Acknowledge Bus Cycle
Address Bus, 7-1
Address Collisions, 7-43
Address Error, 7-6, 7-43, 8-8
Address Registers, 1-8, 2-4
Addressing Modes, 1-10, 2-5, 10-3, 10-4
Address Translation, 3-1
Address Translation Cache, 1-4, 3-2, 3-3, 3-4,
Address Translation Cache Entry, 3-15, 3-30, 4-2
Airflow, 11-29, 11-31
Alternate Bus Master, 4-1, 4-8, 4-9, 5-4, 5-5, 5-8,
Arithmetic Floating-Point Exceptions,
Automatic Test Pattern Generation (ATPG), 6-5
Autovector, 7-33, 7-34
Boundary Scan Control, 6-6, 6-9
Breakpoint Operations, 8-12
BSDL Description, 6-15
MOTOROLA
Field Definitions, B-6–B-7
7-43, 8-20, 9-21, A-6, A-7, B-11
Breakpoint Operation, 7-29, 7-35, 9-20
Interrupt Operation, 5-12, 7-31,
Brief Extension Word Format, 10-7
Full Extension Word Format, 10-7
Index Scaling, 1-9, 1-10
Index Sizing, 1-9, 1-10
Memory Indirect, 2-2
Postincrement, 1-9
Predecrement, 1-9
Program Counter Indirect, 1-9, 1-10
Program Counter Relative, 7-6
Register Indirect, 1-9, 1-10
3-7, 3-26, 5-8, 5-14, 8-7, 8-18
Field Definitions, 3-27, 3-28
5-9
see Floating-Point Exceptions
Bus Cycle, 7-29, 7-35, 9-20
7-29–7-35, 8-2
–A–
–B–
Freescale Semiconductor, Inc.
For More Information On This Product,
M68040 USER’S MANUAL
Go to: www.freescale.com
INDEX
Buffer Selection, 7-69
Burst Mode Operations, 4-3, 4-11, 5-9
Burst Bus Cycles, see Bus Cycles
Burst-Inhibited Bus Cycles, see Bus Cycles
Bus Arbitration, 7-44–7-58
Bus Arbitration States, 7-46–7-49
Bus Controller, 1-5, 7-6, 7-10, 7-13, 7-20, 7-45,
Bus Cycles,
Bus Error, 3-22, 3-30, 4-12, 7-37, 7-42,7-43,
Bus Operations
Bus Synchronization, 7-44
BYPASS, 6-3
Byte Enable Signals, 7-4
Byte Offset, 7-3
Disregard Request Condition, 7-50
Indeterminate Condition, 7-49, 7-58
Explicit Bus Ownership, 7-45
Implicit Bus Ownership, 7-67
with Direct Memory Access, 7-56
8-7, 10-8
Burst, 5-9, 7-9, 7-10, 7-12, 7-13, 7-22, 7-37,
Burst-Inhibited, 7-13, 7-22, 7-42, 7-45, 7-60
Line, 7-4, 7-9
Line Write, 7-22
Locked, 5-7, 7-49, 7-53, 7-55, 8-8
Push, 4-13
Read, 7-4, 7-10, 7-12, 7-32
Read-Modify-Write, 3-21, 7-26, 7-41, 7-45, see
Write, 7-4, 7-20
9-21
Access Serialization, 7-44
Synchronization, 7-44
Conditional Branch, 7-50
Data Cache, 7-44
Double Bus Fault, 8-8, 8-18
Exceptions, 8-8
Interrupt Pending Procedure, 7-30
Locked Transfer, 8-8
Misaligned Access, 4-3, 4-11, 10-3
Misaligned Operand, 7-6, 7-37
Relinquish and Retry, 4-12, 7-41, 7-42, 7-55
Reset, 7-66
PAL Equation, 7-4
7-38, 7-42, 7-70
also Bus Cycles, Locked
INDEX-1