Z8F1233QH020SG Zilog, Z8F1233QH020SG Datasheet - Page 56
![IC ENCORE XP MCU FLSH 12K 20QFN](/photos/12/23/122392/20-qfn-pc_sml.jpg)
Z8F1233QH020SG
Manufacturer Part Number
Z8F1233QH020SG
Description
IC ENCORE XP MCU FLSH 12K 20QFN
Manufacturer
Zilog
Series
Encore!®r
Specifications of Z8F1233QH020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, LED, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
For Use With
770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Other names
269-4656
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8F1233QH020SG
Manufacturer:
Zilog
Quantity:
670
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Table 19. Port A–D Alternate Function Subregisters (PxAF)
Table 20. Port A–D Output Control Subregisters (PxOC)
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS025111-1207
Caution:
POC7
R/W
AF7
If 02H in Port A–D Address Register, accessible through the Port A–D Control Register
If 03H in Port A–D Address Register, accessible through the Port A–D Control Register
7
7
0
AF[7:0]—Port Alternate function enabled
0 = The port pin is in NORMAL mode and the DDx bit in the Port A–D data direction
subregister determines the direction of the pin.
1 = The Alternate function selected through Alternate function set subregisters is enabled.
Port pin operation is controlled by the Alternate function.
Port A–D Output Control Subregisters
The Port A–D output control subregister is accessed through the Port A–D control register
by writing
A–D output control subregisters to 1, configures the specified port pins for open-drain
operation. These subregisters affect the pins directly and, as a result, Alternate functions
are also affected.
POC[7:0]—Port output control
These bits function independently of the Alternate function bit and always disable the
drains, if set to 1.
0 = The drains are enabled for any OUTPUT mode (unless overridden by the Alternate
function).
1 = The drain of the associated pin is disabled (OPEN-DRAIN mode).
Do not enable Alternate functions for GPIO port pins for which there is no
associated Alternate function. Failure to follow this guideline can result in
unpredictable operation.
POC6
R/W
AF6
03H
6
6
0
to the Port A–D address register. See
POC5
R/W
AF5
5
5
0
00H (Ports A–C); 01H (Port D)
POC4
R/W
AF4
4
4
0
R/W
POC3
R/W
AF3
3
3
0
Table
POC2
R/W
AF2
20. Setting the bits in the Port
Z8 Encore!
2
2
0
General Purpose Input/Output
Product Specification
POC1
R/W
AF1
1
1
0
®
F0830 Series
POC0
R/W
AF0
0
0
0
46
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