Z8F1233QH020SG Zilog, Z8F1233QH020SG Datasheet - Page 91

• Manufacturer Part Number: Z8F1233QH020SG
• Description: IC ENCORE XP MCU FLSH 12K 20QFN
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F1233QH020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Other names: 269-4656

Table 53. Timer 0–1 Control Register 0 (TxCTL0)
BITS
FIELD
RESET
R/W
ADDR
PS025111-1207
TMODEHI
R/W
7
0
TMODEHI—Timer mode high bit
This bit along with the TMODE field in TxCTL1 register determines the operating mode
of the timer. This is the most significant bit of the timer mode selection value. See the
TxCTL1 register description on the next page for additional details.
TICONFIG—Timer interrupt configuration
This field configures timer interrupt definition.
PWMD—PWM delay value
This field is a programmable delay to control the number of system clock cycles delay
before the timer output and the timer output complement are forced to their Active state.
•
•
•
•
•
•
•
•
INPCAP—Input Capture event
This bit indicates whether the most recent timer interrupt is caused by a timer input
Capture event.
0x = Timer interrupt occurs on all the defined reload, compare and Input events.
10 = Timer interrupt occurs only on defined Input Capture/Deassertion events.
11 = Timer interrupt occurs only on defined Reload/Compare events.
000 = No delay
001 = 2 cycles delay
010 = 4 cycles delay
011 = 8 cycles delay
100 = 16 cycles delay
101 = 32 cycles delay
110 = 64 cycles delay
111 = 128 cycles delay
0 = Previous timer interrupt is not caused by timer input Capture event
1 = Previous timer interrupt is caused by timer input Capture event
R/W
0
6
TICONFIG
R/W
5
0
Reserved
R/W
0
4
F06H, F0EH
R/W
0
3
PWMD
R/W
Z8 Encore!
2
0
Product Specification
R/W
0
®
1
F0830 Series
INPCAP
R/W
Timers
0
0
81