Z8F1233QH020SG Zilog, Z8F1233QH020SG Datasheet - Page 83
Z8F1233QH020SG
Manufacturer Part Number
Z8F1233QH020SG
Description
IC ENCORE XP MCU FLSH 12K 20QFN
Manufacturer
Zilog
Series
Encore!®r
Specifications of Z8F1233QH020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, LED, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
12KB (12K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
For Use With
770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Other names
269-4656
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8F1233QH020SG
Manufacturer:
Zilog
Quantity:
670
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PS025111-1207
If TPOL is set to 1, the ratio of the PWM output high time to the total period is represented
by:
CAPTURE Mode
In CAPTURE mode, the current timer count value is recorded when the appropriate
external timer input transition occurs. The capture count value is written to the timer
PWM high and low byte registers. The timer input is the system clock. The TPOL bit in
the timer control register determines if the capture occurs on a rising edge or a falling edge
of the timer input signal.
When the Capture event occurs, an interrupt is generated and the timer continues counting.
The INPCAP bit in TxCTL1 register is set to indicate the timer interrupt because of an
input Capture event.
The timer continues counting up to the 16-bit reload value stored in the timer reload high
and low byte registers. On reaching the reload value, the timer generates an interrupt and
continues counting. The INPCAP bit in TxCTL1 register clears, indicating the timer
interrupt is not because of an input Capture event.
Follow the steps below for configuring a timer for CAPTURE mode and initiating the
count:
1. Write to the timer control register to:
2. Write to the timer high and low byte registers to set the starting count value (typically
3. Write to the timer reload high and low byte registers to set the reload value.
4. Clear the timer PWM high and low byte registers to 0000H. Clearing these registers
5. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing
PWM Output High Time Ratio (%)
–
–
–
–
0001H
allows user software to determine if interrupts were generated either by a Capture
event or by a reload. If the PWM high and low byte registers still contain 0000H after
the interrupt, the interrupt were generated by a reload.
to the relevant interrupt registers. By default, the timer interrupt is generated for both
input capture and Reload events. If appropriate, configure the timer interrupt to be
generated only at the input Capture event or the Reload event by setting TICONFIG
field of the TxCTL1 register.
Disable the timer
Configure the timer for CAPTURE mode.
Set the prescale value.
Set the capture edge (rising or falling) for the timer input.
).
=
--------------------------------- -
Reload Value
PWM Value
×
100
Z8 Encore!
Product Specification
®
F0830 Series
Timers
73
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