Z8F1233QH020SG Zilog, Z8F1233QH020SG Datasheet - Page 92

• Manufacturer Part Number: Z8F1233QH020SG
• Description: IC ENCORE XP MCU FLSH 12K 20QFN
• Manufacturer: Zilog
• Series: Encore!®r

Specifications of Z8F1233QH020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Other names: 269-4656

Table 54. Timer 0–1 Control Register 1 (TxCTL1)
BITS
FIELD
RESET
R/W
ADDR
PS025111-1207
TEN
R/W
0
7
Timer 0–1 Control Register 1
The timer 0–1 control (TxCTL1) registers enable/disable the timers, set the prescaler
value, and determine the timer operating mode.
TEN—Timer enable
0 = Timer is disabled.
1 = Timer enabled to count.
TPOL—Timer input/output polarity
Operation of this bit is a function of the current operating mode of the timer.
ONE-SHOT Mode
When the timer is disabled, the timer output signal is set to the value of this bit. When
the timer is enabled, the timer output signal is complemented on timer reload.
CONTINUOUS Mode
When the timer is disabled, the timer output signal is set to the value of this bit. When
the timer is enabled and reloaded, the timer output signal is complemented.
COUNTER Mode
If the timer is disabled, the timer output signal is set to the value of this bit.
If the timer is enabled the timer output signal is complemented after timer reload.
0 = Count occurs on the rising edge of the timer input signal.
1 = Count occurs on the falling edge of the timer input signal.
PWM SINGLE OUTPUT Mode
0 = Timer output is forced low (0), when the timer is disabled. The timer output is
forced high (1), when the timer is enabled and the PWM count matches and the timer
output is forced low (0), when the timer is enabled and reloaded.
1 = Timer output is forced high (1), when the timer is disabled. The timer output is
forced low(0), when the timer is enabled and the PWM count matches and forced high
(1) when the timer is enabled and reloaded.
CAPTURE Mode
0 = Count is captured on the rising edge of the timer input signal.
1 = Count is captured on the falling edge of the timer input signal.
TPOL
R/W
6
0
R/W
5
0
PRES
R/W
0
4
F07H, F0FH
R/W
3
0
R/W
Z8 Encore!
0
2
Product Specification
TMODE
R/W
1
0
®
F0830 Series
R/W
0
0
Timers
82