ATTINY4313-MU Atmel, ATTINY4313-MU Datasheet

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... Idle Mode • 24 µA at 1.8V and 1MHz – Power-down Mode • 0.1 µA at 1.8V and +25°C ® 8-Bit Microcontroller 8-bit Microcontroller with 2/4K Bytes In-System Programmable Flash ATtiny2313A ATtiny4313 Preliminary Rev. 8246A–AVR–11/09 ...

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Pin Configurations Figure 1-1. 1.1 Pin Descriptions 1.1.1 VCC Digital supply voltage. 1.1.2 GND Ground. 1.1.3 Port A (PA2..PA0) Port 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output ...

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The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ...

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Overview The ATtiny2313A/4313 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny2313A/4313 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to ...

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... The ATtiny2313A/4313 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emu- lators, and Evaluation kits. 2.2 Comparison Between ATtiny2313A and ATtiny4313 The ATtiny2313A and ATtiny4313 differ only in memory sizes. ent memory sizes for the two devices. Table 2-1. Device ATtiny2313A ATtiny4313 8246A– ...

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... About 3.1 Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation ...

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CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle ...

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Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look ...

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The AVR Status Register – SREG – is defined as: Bit 0x3F (0x5F) Read/Write Initial Value • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual ...

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Two 8-bit output operands and one 8-bit result input • Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Figure 4-2 Figure 4-2. Most of the instructions operating on ...

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In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 4.5 Stack Pointer The Stack is mainly used for storing temporary data, for storing local ...

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Figure 4-4. 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Execute Figure 4-5 operation using two register operands is executed, and the result is stored back to the destina- tion register. Figure 4-5. Register Operands Fetch ALU ...

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Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding interrupt flag(s) ...

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Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini- mum. After four clock cycles the program vector address for the actual interrupt handling routine is executed. During this four clock ...

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Memories This section describes the different memories in the ATtiny2313A/4313. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATtiny2313A/4313 features an EEPROM Memory for data storage. All three ...

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SRAM Data Memory Figure 5-2 The lower 224/352 data memory locations address both the Register File, the I/O memory, Extended I/O memory, and the internal data SRAM. The first 32 locations address the Register File, the next 64 location ...

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Figure 5-3. 5.3 EEPROM Data Memory The ATtiny2313A/4313 contains 128/256 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least ...

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EEPMn bits are zero, writing EEPE (within four cycles after EEMPE is written) will trigger the erase/write operation. Both the erase and write cycle are done in one operation and the total programming time is given in and write operations ...

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Program Examples The following code examples show one assembly and one C function for erase, write, or atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will ...

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The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: ; Wait for completion ...

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... Initial Value • Bit 7 – EEAR7: EEPROM Address This is the most significant EEPROM address bit of ATtiny4313. In devices with less EEPROM, i.e. ATtiny2313A, this bit is reserved and will always read zero. The initial value of the EEPROM Address Register (EEAR) is undefined and a proper value must therefore be written before the EEPROM is accessed. • ...

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EEDR – EEPROM Data Register Bit 0x1D (0x3D) Read/Write Initial Value • Bits 7..0 – EEDR7..0: EEPROM Data For the EEPROM write operation the EEDR Register contains the data to be written to the EEPROM in the address given ...

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When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the ...

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Clock System Figure 6-1 need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in ment and Sleep ...

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Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Table 6-1. ...

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... OSCCAL Register and thereby automatically calibrates the RC Oscillator and 25°C, this calibration gives a frequency within ± 10% of the nominal frequency. Using calibration methods as described in application notes available at www.atmel.com/avr it is possi- ble to achieve ± 2% accuracy at any given V as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the ...

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Reset Time-out. For more information on the pre-programmed calibration value, see the section “Calibration Byte” on page Table 6-3. Note: When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 6-4. Table 6-4. ...

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Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively inverting amplifier which can be con- figured for use as an On-chip Oscillator, as shown in crystal or a ceramic resonator may be used. C1 and C2 ...

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Table 6-7. CKSEL0 Notes: 6.3 System Clock Prescaler The ATtiny2313A/4313 has a system clock prescaler, and the system clock can be divided by setting the decrease the system clock frequency and the ...

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Clock Output Buffer The device can output the system clock on the CLKO pin. To enable the output, the CKOUT fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir- ...

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The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles ...

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Table 6-9. CLKPS3 ATtiny2313A/4313 32 Clock Prescaler Select (Continued) CLKPS2 CLKPS1 CLKPS0 Clock Division Factor 1 Reserved 0 Reserved 1 Reserved 8246A–AVR–11/09 ...

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Power Management and Sleep Modes The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low power applications. In addition, sleep modes enable the application to shut down unused modules in the MCU, ...

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Control and Status Register” on page mode. 7.1.2 Power-Down Mode When the SM1:0 bits are written to 01/11, the SLEEP instruction makes the MCU enter Power- down mode. In this mode, the Oscillator is stopped, while the external interrupts, ...

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Peripheral shutdown can be used in Idle mode and Active mode to significantly reduce the over- all power consumption. See sleep modes, the clock is already stopped. 7.4 Minimizing Power Consumption There are several issues to consider when trying to ...

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For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to V input buffers can be disabled by writing to the Digital Input Disable Register (DIDR). See – Digital Input Disable ...

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Bit 2 – PRTIM0: Power Reduction Timer/Counter0 Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown. • Bit 1 – PRUSI: Power Reduction USI ...

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System Control and Reset 8.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP ...

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Reset Sources The ATtiny2313A/4313 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is ...

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External Reset An External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longer than the minimum pulse width (see ate a reset, even if the clock is not running. Shorter pulses are ...

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Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t “Interrupts” on page 47 ...

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The Watchdog Timer can also be configured to generate an interrupt instead of a reset. This can be very helpful when using the Watchdog to wake-up from Power-down. To prevent unintentional disabling of the Watchdog or unintentional change of time-out ...

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In the same operation, write a logical one to WDCE and WDE. Even though the b. Within the next four clock cycles, in the same operation, write the WDP bits as 8.4.2 Code Example The following code example shows ...

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Register Description 8.5.1 MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU Reset. Bit 0x34 (0x54) Read/Write Initial Value • Bits 7..4 – Res: Reserved Bits These bits are reserved ...

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To avoid the Watchdog Reset, WDIE must be set after each interrupt. Table 8-2. WDE • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when ...

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Table 8-3. WDP3 Note: ATtiny2313A/4313 46 Watchdog Timer Prescale Select Number of WDT Oscillator WDP2 WDP1 WDP0 ...

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Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny2313A/4313. For a general explanation of the AVR interrupt handling, refer to on page 9.1 Interrupt Vectors The interrupt vectors of ATtiny2313A/4313 are described in Table ...

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The most typical and general setup for the Interrupt Vector Addresses in ATtiny2313A/4313 shown below: Address Labels Code 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 ; ...

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Low Level Interrupt A low level interrupt on INT0 or INT1 is detected asynchronously. This means that the interrupt source can be used for waking the part also from sleep modes other than Idle (the I/O clock is halted ...

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Register Description 9.3.1 MCUCR – MCU Control Register The External Interrupt Control Register contains control bits for interrupt sense control. Bit 0x35 (0x55) Read/Write Initial Value • Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 ...

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Bits 2..0 – Res: Reserved Bits These bits are reserved and will always read as zero. • Bit 7 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status ...

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Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT1 is configured as a level interrupt. • Bit 6 – INTF0: External Interrupt Flag 0 When an edge or logic ...

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Bits 7:3 – Res: Reserved Bits These bits are reserved and will always read as zero. • Bits 2..0 – PCINT10..8: Pin Change Enable Mask 10..8 Each PCINT10..8 bit selects whether pin change interrupt is enabled on the corresponding ...

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I/O-Ports All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI ...

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Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. tional description of one I/O-port pin, here generically called Pxn. Figure 10-2. General Digital I/O Note: 10.1.1 Configuring the Pin Each port pin consists ...

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Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 10.1.3 Switching Between ...

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Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the ...

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Connecting unused pins directly to V accidentally configured as an output. 10.1.7 Program Examples The following code example shows how to set port A pins 0 and 1 high, ...

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Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. In below is shown how the port pin control signals from the simplified be overridden by alternate functions. Figure 10-5. Alternate Port Functions ...

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Table 10-2 ure 10-5 in the modules having the alternate function. Table 10-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for each port, and relate the ...

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Alternate Functions of Port A The Port A pins with alternate function are shown in Table 10-3. • Port A, Bit 0 – XTAL1/CLKI/PCINT8 • XTAL1: Chip Clock Oscillator pin 1. Used for all chip clock sources except internal ...

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Table 10 page Table 10-4. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Notes: 10.2.2 Alternate Functions of Port B The Port B pins with alternate function are shown in Table 10-5. ATtiny2313A/4313 ...

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Table 10-5. • Port B, Bit 0 – AIN0/PCINT0 • AIN0: Analog Comparator Positive input. Configure the port pin as input with the internal pull- up switched off to avoid the digital port function from interfering with the function of ...

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The OC1B pin is also the output pin for the PWM mode timer function. • PCINT4: Pin Change Interrupt Source 4. The PB4 pin can serve as an external interrupt source for pin change interrupt ...

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Table 10-6. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Table 10-7. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 8246A–AVR–11/09 Overriding Signals for Alternate Functions in PB7..PB4 PB7/USCK/ SCL/PCINT7 ...

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Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 10-8. • Port D, Bit 0 – RXD/PCINT11 • RXD: UART Data Receiver. • PCINT11: Pin Change Interrupt Source 11. The PD0 pin ...

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Port D, Bit 4 – T0/PCINT15 • T0: Timer/Counter0 External Counter Clock input is enabled by setting (one) the bits CS02 and CS01 in the Timer/Counter0 Control Register (TCCR0). • PCINT15: Pin Change Interrupt Source 15. The PD4 pin ...

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Table 10-10. Overriding Signals for Alternate Functions in PD3..PD0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 10.3 Register Description 10.3.1 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value • Bit 7 ...

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PINA – Port A Input Pins Address Bit 0x19 (0x39) Read/Write Initial Value 10.3.5 PORTB – Port B Data Register Bit 0x18 (0x38) Read/Write Initial Value 10.3.6 DDRB – Port B Data Direction Register Bit 0x17 (0x37) Read/Write Initial ...

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Timer/Counter0 with PWM 11.1 Features • Two Independent Output Compare Units • Double Buffered Output Compare Registers • Clear Timer on Compare Match (Auto Reload) • Glitch Free, Phase Correct Pulse Width Modulator (PWM) • Variable PWM Period ...

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The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk The double buffered Output Compare Registers (OCR0A and ...

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Signal description (internal signals): count direction clear clk top bottom Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select bits (CS02:0). When no clock source ...

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Figure 11-3. Output Compare Unit, Block Diagram The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou- ble buffering is ...

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Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting. The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of ...

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Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0x1 tells the Waveform Generator that no action on the OC0x Register ...

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Figure 11-5. CTC Mode, Timing Diagram TCNTn OCn (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be ...

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PWM mode is shown in togram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Com- pare Matches between OCR0x and TCNT0. Figure 11-6. Fast PWM ...

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OC0A toggle in CTC mode, except the double buffer feature of the Out- put Compare unit is enabled in the fast PWM mode. 11.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM02:0 = ...

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OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (See visible on the port pin if the data direction for the port pin is ...

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Figure 11-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk I/O TCNTn TOVn Figure 11-10 mode and PWM mode, where OCR0A is TOP. Figure 11-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f clk clk (clk I/O TCNTn ...

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Register Description 11.9.1 TCCR0A – Timer/Counter Control Register A Bit 0x30 (0x50) Read/Write Initial Value • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of ...

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Table 11-4 rect PWM mode. Table 11-4. COM0A1 Note: • Bits 5:4 – COM0B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits ...

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Table 11-7 rect PWM mode. Table 11-7. COM0B1 Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the ATtiny2313A/4313 and will always read as zero. • Bits 1:0 – WGM01:0: ...

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TCCR0B – Timer/Counter Control Register B Bit 0x33 (0x53) Read/Write Initial Value • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility ...

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Table 11-9. CS02 external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature ...

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TIMSK – Timer/Counter Interrupt Mask Register Bit 0x39 (0x59) Read/Write Initial Value • Bit 4 – Res: Reserved Bit This bit is reserved bit in the ATtiny2313A/4313 and will always read as zero. • Bit 2 – OCIE0B: Timer/Counter0 ...

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The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Generation Mode Bit Description” on page • Bit 0 – OCF0A: Output Compare Flag 0 A The OCF0A bit is set when a Compare Match occurs ...

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Timer/Counter1 12.1 Features • True 16-bit Design (i.e., Allows 16-bit PWM) • Two independent Output Compare Units • Double Buffered Output Compare Registers • One Input Capture Unit • Input Capture Noise Canceler • Clear Timer on Compare ...

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Most register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit channel. However, when using the register or bit defines ...

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Compatibility The 16-bit Timer/Counter has been updated and improved from previous versions of the 16-bit AVR Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier version regarding: • All 16-bit Timer/Counter related I/O Register address locations, including Timer ...

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TOP BOTTOM The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) con- taining the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight bits. The TCNT1H Register can only ...

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Figure 12-3. Input Capture Unit Block Diagram When a change of the logic level (an event) occurs on the Input Capture pin (ICP1), alternatively on the Analog Comparator output (ACO), and this change confirms to the setting of the edge ...

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Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs are sampled using the same technique as for the T1 pin identical. However, when the noise canceler is enabled, additional logic is inserted before the edge detector, ...

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A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e., counter resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the Waveform Generator. Figure ...

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For more information of how to access the 16-bit registers refer to on page 12.6.1 Force Output Compare In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output ...

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Figure 12-5. Compare Match Output Unit, Schematic COMnx1 COMnx0 FOCnx clk The general I/O port function is overridden by the Output Compare (OC1x) from the Waveform Generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction ...

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The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM1x1:0 bits control whether the PWM out- put generated should be inverted or not (inverted or non-inverted PWM). ...

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Figure 12-6. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 flag according to the register used to define ...

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The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the max- imum resolution is 16-bit ...

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The OCR1A Register however, is double buffered. This feature allows the OCR1A I/O location to be written anytime. When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The OCR1A Compare Register ...

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OCR1A set to MAX). The PWM resolu- tion in bits can be calculated by using the following equation: In phase correct PWM mode the counter is incremented until the counter value ...

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TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period ...

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In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and ...

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PWM output can be generated by setting the COM1x1:0 to three (See page 111). The actual OC1Fx value will only be visible on the port pin if the data direction for the port pin is set as output ...

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Figure 12-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f Figure 12-12 on page 105 using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should ...

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Figure 12-13. Timer/Counter Timing Diagram, with Prescaler (f and ICF n 12.10 Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must ...

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OCR1A/B and ICR1 Registers. Note that when using “C”, the compiler handles the 16-bit access. Assembly Code Examples C Code Examples Note: The assembly code example returns the TCNT1 value in the r17:r16 register pair important to ...

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The following code examples show how atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example TIM16_ReadTCNT1: ; Save global interrupt ...

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The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNT1: C Code Example void ...

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Register Description 12.11.1 TCCR1A – Timer/Counter1 Control Register A Bit 0x2F (0x4F) Read/Write Initial Value • Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A • Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B The COM1A1:0 ...

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Table 12-4 correct or the phase and frequency correct, PWM mode. Table 12-4. COM1A1/COM1B1 Note: • Bit 1:0 – WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence of ...

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Table 12-5. Waveform Generation Mode Bit Description WGM12 WGM11 Mode WGM13 (CTC1) (PWM11 ...

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When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Cap- ture function is disabled. • Bit 5 – Reserved ...

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A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. 12.11.4 TCNT1H and TCNT1L – Timer/Counter1 ...

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The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. ...

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Bit 6 – OCF1A: Timer/Counter1, Output Compare A Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register A (OCR1A). Note that a Forced Output Compare (FOC1A) strobe ...

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Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 13.1 Internal Clock Source The Timer/Counter can be clocked directly ...

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Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise risk that a false Timer/Counter clock pulse is generated. Each half period of the ...

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USART 14.1 Features • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with ...

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The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control registers are shared by all units. The Clock Generation logic consists of synchronization logic for ...

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Figure 14-2. Clock Generation Logic, Block Diagram Signal description: txclk rxclk xcki xcko fosc 14.3.1 Internal Clock Generation – The Baud Rate Generator Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The description ...

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Table 14-1. Operating Mode Asynchronous Normal mode (U2X = 0) Asynchronous Double Speed mode (U2X = 1) Synchronous Master mode Note: BAUD f OSC UBRR Some examples of UBRR values for some system clock frequencies are found in (see page ...

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Synchronous Clock Operation When synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is ...

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P Sp IDLE The frame format used by the USART is set by the UCSZ2:0, UPM1:0 and USBS bits in UCSRB and UCSRC. The Receiver and Transmitter use the same setting. Note that changing the setting of any of ...

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The following simple USART initialization code examples show one assembly and one C func- tion that are equal in functionality. The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. The baud rate is given ...

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Sending Frames with Data Bit A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The CPU can load the transmit buffer by writing to the UDR I/O location. The ...

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Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the low byte of the character is written to UDR. The following ...

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Shift Register. For compat- ibility with future devices, always write this bit to zero when writing the UCSRA Register. When the Data Register Empty Interrupt Enable (UDRIE) ...

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Data Reception – The USART Receiver The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Regis- ter to one. When the Receiver is enabled, the normal pin operation of the RxD pin is ...

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FIFO and consequently the TXB8, FE, DOR and UPE bits, which all are stored in the FIFO, will change. The following code example shows a simple USART receive function that handles both nine ...

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The receive function example reads all the I/O Registers into the Register File before any com- putation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early ...

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Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and ...

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Normal mode, and eight times the baud rate for Double Speed mode. The hor- izontal arrows illustrate the synchronization variation due to the sampling process. Note the larger time variation when using the Double Speed mode ...

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Figure 14-7 of the next frame. Figure 14-7. Stop Bit Sampling and Next Start Bit Sampling Sample (U2X = 0) Sample (U2X = 1) The same majority voting is done to the stop bit as done for the other bits ...

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Table 14-2. # (Data+Parity Bit) Table 14-3. # (Data+Parity Bit) The recommendations of the maximum receiver baud rate error was made under the assump- tion that the Receiver and Transmitter equally divides the maximum total error. There are two possible ...

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When the frame type bit is zero the frame is a data frame. The Multi-processor Communication mode enables several slave MCUs to ...

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For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to zero by the Receiver. The transmit buffer can only be written when the UDRE flag in the UCSRA Register is set. ...

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Bit 2 – UPE: USART Parity Error This bit is set if the next character in the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPM1 = 1). This bit ...

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Bit 2 – UCSZ2: Character Size The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data bits (Char- acter SiZe frame the Receiver and Transmitter use. • Bit 1 – RXB8: Receive ...

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Bit 3 – USBS: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. Table 14-6. • Bit 2:1 – UCSZ1:0: Character Size The UCSZ1:0 bits combined ...

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Bit 15:12 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when UBRRH is written. • Bit 11:0 – UBRR11:0: USART Baud Rate Register This is ...

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Table 14-10. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 3.6864 MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRR Error UBRR 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% ...

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Table 14-11. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 8.0000 MHz osc Baud U2X = 0 Rate (bps) UBRR Error UBRR 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% 103 14.4k 34 ...

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Table 14-12. Examples of UBRR Settings for Commonly Used Oscillator Frequencies Baud Rate (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 0.5M 1M (1) Max. 1. ATtiny2313A/4313 144 (Continued) U2X = 0 UBRR Error 416 ...

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USART in SPI Mode 15.1 Features • Full Duplex, Three-wire Synchronous Data Transfer • Master Operation • Supports all four SPI Modes of Operation (Mode and 3) • LSB First or MSB First Data Transfer (Configurable ...

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Table 15-1. Operating Mode Synchronous Master mode Note: BAUD f OSC UBRR 15.4 SPI Data Modes and Timing There are four combinations of XCK (SCK) phase and polarity with respect to serial data, which are determined by control bits UCPHA ...

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Frame Formats A serial frame for the MSPIM is defined to be one character of 8 data bits. The USART in MSPIM mode has two valid frame formats: • 8-bit data with MSB first • 8-bit data with LSB ...

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For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. Assembly Code Example USART_Init: clr r18 out UBRRH,r18 out UBRRL,r18 ; Setting the XCK port ...

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Data Transfer Using the USART in MSPI mode requires the Transmitter to be enabled, i.e. the TXEN bit in the UCSRB register is set to one. When the Transmitter is enabled, the normal port operation of the TxD pin ...

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Assembly Code Example USART_MSPIM_Transfer: ; Wait for empty transmit buffer sbis UCSRA, UDRE rjmp USART_MSPIM_Transfer ; Put data (r16) into buffer, sends the data out UDR,r16 ; Wait for data to be received USART_MSPIM_Wait_RXC: sbis UCSRA, RXC rjmp USART_MSPIM_Wait_RXC ; ...

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AVR USART MSPIM vs. AVR SPI The USART in MSPIM mode is fully compatible with the AVR SPI regarding: • Master mode timing diagram. • The UCPOL bit functionality is identical to the SPI CPOL bit. • The UCPHA ...

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Register Description The following section describes the registers used for SPI operation using the USART. 15.8.1 UDR – USART MSPIM I/O Data Register The function and bit description of the USART data register (UDR) in MSPI mode is identical ...

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Bit 6 – TXCIE: TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXC Flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the Global Interrupt ...

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Bit 5:3 – Reserved Bits in MSPI mode When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits must be written to zero when UCSRC is written. • Bit 2 – ...

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USI – Universal Serial Interface 16.1 Features • Two-wire Synchronous Data Transfer (Master or Slave) • Three-wire Synchronous Data Transfer (Master or Slave) • Data Received Interrupt • Wakeup from Idle Mode • In Two-wire Mode: Wake-up from All ...

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The serial input is always sampled from the Data Input (DI) pin independent of the configuration. The 4-bit counter can be both read and written via the ...

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Figure 16-3. Three-wire Mode, Timing Diagram CYCLE USCK USCK DO DI The three-wire mode timing is shown in erence. One bit is shifted into the USI Data Register (USIDR) for each of these cycles. The USCK timing is shown for ...

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SPITransfer_loop: The code is size optimized using only eight instructions (plus return). The code example assumes that the DO and USCK pins have been enabled as outputs in DDRA. The value stored in register r16 prior to the function ...

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SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave: init: ... SlaveSPITransfer: SlaveSPITransfer_loop: The code is size optimized using only eight instructions (plus return). The code example assumes that the ...

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Figure 16-4. Two-wire Mode Operation, Simplified Diagram The data direction is not given by the physical layer. A protocol, like the one used by the TWI- bus, must be implemented to control the data flow. Figure 16-5. Two-wire Mode, Typical ...

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The master set the first bit to be transferred and releases the SCL line (C). The slave samples the data and shifts it into the USI Data Register at the positive edge of the SCL clock. 4. After eight ...

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Alternative USI Usage The flexible design of the USI allows used for other tasks when serial communication is not needed. Below are some examples. 16.4.1 Half-Duplex Asynchronous Data Transfer Using the USI Data Register in three-wire ...

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Data Register can therefore be clocked externally and data input sampled, even when outputs are disabled. Table 16-1. USIWM1 Note: • Bit 3:2 – USICS1:0: Clock Source Select These bits set the clock source for the ...

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Table 16-2 used for the USI Data Register and the 4-bit counter. Table 16-2. USICS1 • Bit 1 – USICLK: Clock Strobe Writing a one to this bit location strobes the USI Data ...

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If USISIE bit in USICR and the Global Interrupt Enable Flag are set, an interrupt will be gener- ated when this flag is set. The flag will only be cleared by writing a logical one to the USISIF bit. Clearing ...

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Note that even when no wire mode is selected (USIWM1 both the external data input (DI/SDA) and the external clock input (USCK/SCL) can still be used by the USI Data Register. The output pin (DO or SDA, depending ...

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Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator ...

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Bit 4 – ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit ...

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On-chip Debug System 18.1 Features • Complete Program Flow Control • Emulates All On-chip Functions, Both Digital and Analog, except RESET Pin • Real-time Operation • Symbolic Debugging Support (Both at C and Assembler Source Level, or for ...

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Pull-Up resistor on the dW/(RESET) line must be larger than 10k. However, the pull-up resistor is optional. • Connecting the RESET pin directly to V • Capacitors inserted on the RESET pin must be disconnected when using debugWire. • ...

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Register Description The following section describes the registers used with the debugWire. 18.6.1 DWDR – debugWire Data Register Bit Read/Write Initial Value The DWDR Register provides a communication channel from the running program in the MCU to the debugger. ...

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Self-Programming the Flash The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associ- ated protocol to read code and write (program) that code ...

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Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page ...

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EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation recommended ...

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To read the Fuse High Byte (FHB), simply replace the address in the Z-pointer with 0x0003 and repeat the procedure above. If successful, the contents of the destination register are as follows. Bit Rd Refer to To read the Fuse ...

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Preventing Flash Corruption During periods of low V too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be ...

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See details. • Bit 4 – CTPB: Clear Temporary Page Buffer If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be cleared and the data will ...

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Memory Programming This section describes the different methods for programming ATtiny2313A/4313 memories. 20.1 Program And Data Memory Lock Bits The ATtiny2313A/4313 provides two Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the ...

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Fuse Bits The ATtiny2313A/4313 has three Fuse bytes. briefly the functionality of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed. Table ...

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Table 20-5. Fuse Low Byte CKDIV8 CKOUT SUT1 SUT0 CKSEL3 CKSEL2 CKSEL1 CKSEL0 Notes: The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if Lock bit1 (LB1) is programmed. Program ...

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... Flash memory). 3. 0x002: 0x0A (indicates ATtiny2313A device when 0x001 is 0x91). For the ATtiny4313 the signature bytes are: 1. 0x000: 0x1E (indicates manufactured by Atmel). 2. 0x001: 0x92 (indicates 4KB Flash memory). 3. 0x002: 0x0D (indicates ATtiny4313 device when 0x001 is 0x92). 20.4 Page Size Table 20-7. Device ...

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Parallel Programming Parameters, Pin Mapping, and Commands This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATtiny2313A/4313. Pulses are assumed least 250 ...

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Table 20-10. Pin Values Used to Enter Programming Mode Table 20-11. XA1 and XA0 Coding XA1 When pulsing WR or OE, the command loaded determines the action executed. The different Commands are shown in Table 20-12. ...

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Wait µs, and apply 11.5 - 12.5V to RESET. 5. Keep the Prog_enable pins unchanged for at least 10µs after the High-voltage has been applied to ensure the Prog_enable Signature has been latched. 6. Wait at ...

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The following procedure describes how to program the entire Flash memory: A. Load Command “Write Flash” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “0001 0000”. This ...

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Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset. Figure 20-2. Addressing the Flash Which is Organized in Pages Note: Figure 20-3. Programming the Flash Waveforms RDY/BSY RESET +12V Note: 20.6.5 Programming ...

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B: Load Address Low Byte (0x00 - 0xFF Load Data (0x00 - 0xFF). J: Repeat 3 through 4 until the entire buffer is filled. K: Program EEPROM page 1. Set BS1 to “0”. 2. Give WR a ...

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Programming the Fuse Low Bits The algorithm for programming the Fuse Low bits is as follows (refer to on page 184 1. A: Load Command “0100 0000” Load Data Low Byte. Bit n = “0” programs and ...

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Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to page 184 1. A: Load Command “0010 0000” Load Data Low Byte. Bit n = “0” programs the Lock bit. If ...

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Reading the Calibration Byte The algorithm for reading the Calibration byte is as follows (refer to page 184 1. A: Load Command “0000 1000” Load Address Low Byte, 0x00. 3. Set OE to “0”, and BS1 to ...

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Serial Programming Pin Mapping Table 20-13. Pin Mapping Serial Programming 20.8.1 Serial Programming Algorithm When writing serial data to the ATtiny2313A/4313, data is clocked on the rising edge of SCK. When reading data from the ATtiny2313A/4313, data is clocked ...

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Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO the end of the programming session, ...

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Serial Programming Instruction Set Table 20-15. Serial Programming Instruction Set Instruction Byte 1 Programming Enable 1010 1100 Chip Erase 1010 1100 Read Program Memory 0010 H000 Load Program Memory Page 0100 H000 Write Program Memory Page 0100 1100 Read ...

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Table 20-15. Serial Programming Instruction Set Instruction Byte 1 Read Extended Fuse Bits 0101 0000 Read Calibration Byte 0011 1000 Poll RDY/BSY 1111 0000 Note address high bits address low bits Low ...

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Electrical Characteristics 21.1 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0. Voltage on RESET with respect to Ground......-0.5V to +13.0V ...

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T = -40°C to 85° 1.8V to 5.5V (unless otherwise noted) (Continued Symbol Parameter Power Supply Current I CC Power-down mode Notes: 1. “Min” means the lowest value where the pin is guaranteed to be read ...

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Clock Characteristics 21.4.1 Calibrated Internal RC Oscillator Accuracy It is possible to manually calibrate the internal oscillator to be more accurate than default factory calibration. Note that the oscillator frequency depends on temperature and voltage. Voltage and temperature characteristics ...

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System and Reset Characteristics Table 21-3. Symbol V RST t RST V HYST t BOD Notes: 21.5.1 Enhanced Power-On Reset Table 21-4. Symbol V POR V POA SR ON Notes: 21.5.2 Brown-Out Detection ...

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Analog Comparator Characteristics Table 21-6. Analog Comparator Characteristics, T Symbol Parameter V Input Offset Voltage ACIO I Input Leakage Current ACLK Analog Propagation Delay (from saturation to slight overdrive) t ACPD Analog Propagation Delay (large step change) t Digital ...

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Parallel Programming Characteristics Table 21-7. Symbol DVXH t XLXH t XHXL t XLDX t XLWL t XLPH t PLXH t BVPH t PHPL t PLBX t WLBX t PLWL t BVWL t WLWH t ...