ATTINY4313-MU Atmel, ATTINY4313-MU Datasheet - Page 154
![IC MCU AVR 4K FLASH 20QFN](/photos/6/87/68751/313-20-qfn_sml.jpg)
ATTINY4313-MU
Manufacturer Part Number
ATTINY4313-MU
Description
IC MCU AVR 4K FLASH 20QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY4313-MU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
Processor Series
ATtiny
Core
AVR
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI, USART, USI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
18
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY4313-MU
Manufacturer:
HITTITE
Quantity:
101
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• Bit 5:3 – Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,
these bits must be written to zero when UCSRC is written.
• Bit 2 – UDORD: Data Order
When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the
data word is transmitted first. Refer to the Frame Formats section page 4 for details.
• Bit 1 – UCPHA: Clock Phase
The UCPHA bit setting determine if data is sampled on the leasing edge (first) or tailing (last)
edge of XCK. Refer to the SPI Data Modes and Timing section page 4 for details.
• Bit 0 – UCPOL: Clock Polarity
The UCPOL bit sets the polarity of the XCK clock. The combination of the UCPOL and UCPHA
bit settings determine the timing of the data transfer. Refer to the SPI Data Modes and Timing
section page 4 for details.
15.8.5
UBRRL and UBRRH – USART MSPIM Baud Rate Registers
The function and bit description of the baud rate registers in MSPI mode is identical to normal
USART operation. See “UBRRL and UBRRH – USART Baud Rate Registers” on page 140.
ATtiny2313A/4313
154
8246A–AVR–11/09
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