ATTINY4313-MU Atmel, ATTINY4313-MU Datasheet - Page 37

• Manufacturer Part Number: ATTINY4313-MU
• Description: IC MCU AVR 4K FLASH 20QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY4313-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Processor Series: ATtiny
• Core: AVR
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI, USART, USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

7.5.3
8246A–AVR–11/09
BODCR – Brown-Out Detector Control Register
• Bit 2 – PRTIM0: Power Reduction Timer/Counter0
Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0
is enabled, operation will continue like before the shutdown.
• Bit 1 – PRUSI: Power Reduction USI
Writing a logic one to this bit shuts down the USI by stopping the clock to the module. When
waking up the USI again, the USI should be re initialized to ensure proper operation.
• Bit 0 – PRUSART: Power Reduction USART
Writing a logic one to this bit shuts down the USI by stopping the clock to the module. When
waking up the USI again, the USI should be re initialized to ensure proper operation.
The BOD Control Register contains control bits for disabling the BOD by software.
• Bit 1 – BODS: BOD Sleep
In order to disable BOD during sleep the BODS bit must be written to logic one. This is controlled
by a timed sequence and the enable bit, BODSE. First, both BODS and BODSE must be set to
one. Second, within four clock cycles, BODS must be set to one and BODSE must be set to
zero. The BODS bit is active three clock cycles after it is set. A sleep instruction must be exe-
cuted while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit
is automatically cleared after three clock cycles.
• Bit 0 – BODSE: BOD Sleep Enable
The BODSE bit enables setting of BODS control bit, as explained on BODS bit description. BOD
disable is controlled by a timed sequence.
Bit
0x07 (0x27)
Read/Write
Initial Value
—
R
7
0
—
R
6
0
—
R
5
0
—
R
4
0
—
R
3
0
—
R
2
0
BODS
R/W
1
0
BODSE
R/W
0
0
BODCR
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