ATTINY4313-MU Atmel, ATTINY4313-MU Datasheet - Page 176

• Manufacturer Part Number: ATTINY4313-MU
• Description: IC MCU AVR 4K FLASH 20QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY4313-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Processor Series: ATtiny
• Core: AVR
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI, USART, USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 2
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

19.7
19.8
19.9
19.9.1
176
Preventing Flash Corruption
Programming Time for Flash when Using SPM
Register Description
ATtiny2313A/4313
SPMCSR – Store Program Memory Control and Status Register
During periods of low V
too low for the CPU and the Flash to operate properly. These issues are the same as for board
level systems using the Flash, and the same design solutions should be applied.
A Flash program corruption can be caused by two situations when the voltage is too low. First, a
regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,
the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions
is too low.
Flash corruption can easily be avoided by following these design recommendations (one is
sufficient):
The calibrated RC Oscillator is used to time Flash accesses.
gramming time for Flash accesses from the CPU.
Table 19-1.
Note:
The Store Program Memory Control and Status Register contains the control bits needed to con-
trol the Program memory operations.
• Bits 7, 6 – Res: Reserved Bits
These bits are reserved bits in the ATtiny2313A/4313 and always read as zero.
• Bit 5 – RSIG: Read Device Signature Imprint Table
Issuing an LPM instruction within three cycles after RSIG and SPMEN bits have been set in
SPMCSR will return the selected data (depending on Z-pointer value) from the device signature
Bit
0x37 (0x57)
Read/Write
Initial Value
Flash write (Page Erase, Page Write,
and write Lock bits by SPM)
1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
2. Keep the AVR core in Power-down sleep mode during periods of low V
This can be done by enabling the internal Brown-out Detector (BOD) if the operating
voltage matches the detection level. If not, an external low V
can be used. If a reset occurs while a write operation is in progress, the write operation
will be completed provided that the power supply voltage is sufficient.
vent the CPU from attempting to decode and execute instructions, effectively protecting
the SPMCSR Register and thus the Flash from unintentional writes.
1. The min and max programming times is per individual operation.
SPM Programming Time
Symbol
R
7
–
0
CC
R
6
–
0
, the Flash program can be corrupted because the supply voltage is
RSIG
R/W
5
0
Min Programming Time
(1)
CTPB
R/W
4
0
3.7 ms
RFLB
R/W
3
0
PGWRT
R/W
2
0
Table 19-1
Max Programming Time
CC
PGERS
reset protection circuit
R/W
1
0
4.5 ms
shows the typical pro-
CC
SPMEN
R/W
. This will pre-
0
0
8246A–AVR–11/09
SPMCSR