ATTINY4313-MU Atmel, ATTINY4313-MU Datasheet - Page 65
![IC MCU AVR 4K FLASH 20QFN](/photos/6/87/68751/313-20-qfn_sml.jpg)
ATTINY4313-MU
Manufacturer Part Number
ATTINY4313-MU
Description
IC MCU AVR 4K FLASH 20QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY4313-MU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
Processor Series
ATtiny
Core
AVR
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI, USART, USI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
18
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY4313-MU
Manufacturer:
HITTITE
Quantity:
101
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8246A–AVR–11/09
Table 10-6.
Table 10-7.
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
PB7/USCK/
SCL/PCINT7
USI_TWO_WIRE
0
USI_TWO_WIRE
(USI_SCL_HOLD+
PORTB7)•DDB7
USI_TWO_WIRE •
DDB7
0
USI_PTOE
(PCINT7•PCIE)
+USISIE
1
PCINT7 Input
USCK Input SCL
Input
–
PB3/OC1A/
PCINT3
0
0
0
0
OC1A_PVOE
OC1A_PVOV
0
(PCINT3 • PCIE)
1
PCINT7 Input
–
Overriding Signals for Alternate Functions in PB7..PB4
Overriding Signals for Alternate Functions in PB3..PB0
PB6/DO/PCINT6
0
0
0
0
USI_THREE_WIRE
DO
0
(PCINT6•PCIE)
1
PCINT6 Input
–
PCINT6 Input
PB2/OC0A/
PCINT2
0
0
0
0
OC0A_PVOE
OC0A_PVOV
0
(PCINT2 • PCIE)
1
–
PB5/SDA/
DI/PCINT5
0
0
USI_TWO_WIRE
(SDA + PORTB5)•
DDB5
USI_TWO_WIRE
• DDB5
0
0
(PCINT5•PCIE) +
USISIE
1
PCINT5 Input
SDA Input
DI Input
–
PB1/AIN1/
PCINT1
0
0
0
0
0
0
0
(PCINT1 • PCIE)
1
PCINT5 Input
AIN1
PB4/OC1B/
PCINT4
0
0
0
0
OC1B_PVOE
0OC1B_PVOV
0
(PCINT4•PCIE)
1
PCINT4 Input
–
PB0/AIN0/
PCINT0
0
0
0
0
0
0
0
(PCINT0 • PCIE)
1
PCINT4 Input
AIN0
65
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