PIC17LC756A-08/L Microchip Technology, PIC17LC756A-08/L Datasheet
PIC17LC756A-08/L
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PIC17LC756A-08/L Summary of contents
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... TMR3: 16-bit timer/counter • Two Universal Synchronous Asynchronous Receiver Transmitters (USART/SCI) with independent baud rate generators • Synchronous Serial Port (SSP) with SPI™ and C™ modes (including I C Master mode) 2000 Microchip Technology Inc. PIC17C7XX Pin Diagrams 84 PLCC RH2 13 RH3 ...
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... RF6/AN10 13 RF5/AN9 14 RF4/AN8 15 RF3/AN7 16 RF2/AN6 DS30289B-page 2 60 RA0/INT 59 RB0/CAP1 58 RB1/CAP2 57 RB3/PWM2 56 RB4/TCLK12 55 RB5/TCLK3 54 RB2/PWM1 PIC17C75X OSC2/CLKOUT 50 OSC1/CLKIN RB7/SDO 47 RB6/SCK 46 RA3/SDI/SDA 45 RA2/SS/SCL 44 RA1/T0CKI 48 RA0/INT 47 RB0/CAP1 46 RB1/CAP2 45 RB3/PWM2 44 RB4/TCLK12 43 RB5/TCLK3 42 RB2/PWM1 PIC17C75X OSC2/CLKOUT 39 OSC1/CLKIN RB7/SDO 36 RB6/SCK 35 RA3/SDI/SDA 34 RA2/SS/SCL 33 RA1/T0CKI 2000 Microchip Technology Inc. ...
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... RE1/OE RE2/WR RE3/CAP4 MCLR/V PP TEST RF7/AN11 RF6/AN10 RF5/AN9 RF4/AN8 RF3/AN7 RF2/AN6 RH4/AN12 RH5/AN13 80-Pin TQFP RH2 RH3 RD1/AD9 RD0/AD8 RE0/ALE RE1/OE RE2/WR RE3/CAP4 MCLR/V PP TEST RF7/AN11 RF6/AN10 RF5/AN9 RF4/AN8 RF3/AN7 RF2/AN6 RH4/AN12 RH5/AN13 2000 Microchip Technology Inc 838281 80 797877 PIC17C76X 3334353637383940414243 ...
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... PIC17C7XX DC and AC Characteristics.................................................................................................... 267 22.0 Packaging Information ............................................................................................................................... 281 Appendix A: Modifications ....................................................................................................................................... 287 Appendix B: Compatibility........................................................................................................................................ 287 Appendix C: What’s New ......................................................................................................................................... 288 Appendix D: What’s Changed.................................................................................................................................. 288 Index .......................................................................................................................................................................... 289 On-Line Support .......................................................................................................................................................... 299 Reader Response ....................................................................................................................................................... 300 Product Identification System...................................................................................................................................... 301 DS30289B-page 4 2000 Microchip Technology Inc. ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include lit- erature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2000 Microchip Technology Inc. PIC17C7XX DS30289B-page 5 ...
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... PIC17C7XX NOTES: DS30289B-page 6 2000 Microchip Technology Inc. ...
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... The SLEEP (power-down) mode offers additional power saving. Wake-up from SLEEP can occur through several external and internal interrupts and device RESETS. 2000 Microchip Technology Inc. PIC17C7XX A highly reliable Watchdog Timer with its own on-chip RC oscillator provides protection against software mal- function ...
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... Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes (1) (1) ( 64-pin TQFP 80-pin TQFP 80-pin TQFP 68-pin PLCC 84-pin PLCC 84-pin PLCC 2000 Microchip Technology Inc. ...
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... EPROM locations and configuration options already programmed by the factory. Certain code and prototype verification procedures apply before produc- tion shipments are available. Please contact your local Microchip Technology sales office for more details. 2.4 Serialized Quick-Turnaround Production (SQTP Microchip offers a unique programming service, where a few user defined locations in each device are pro- grammed with different serial numbers ...
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... PIC17C7XX NOTES: DS30289B-page 10 2000 Microchip Technology Inc. ...
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... The ALU is a general purpose arith- metic unit. It performs arithmetic and Boolean functions between data in the working register and any register file. 2000 Microchip Technology Inc. PIC17C7XX The WREG register is an 8-bit working register used for ALU operations. All PIC17CXXX devices have hardware multi- plier ...
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... Control Signals Test Mode Select Test IR Latch <16> Decode F9 ROM Latch <16> 8 AD<15:0> PORTC, PORTD Data Latch Program Memory (EPROM) 17C756A 16K x 16 17C752 ALE, Address WR, Latch OE, PORTE 16 16 10-bit Capture2 SSP A/D Interrupt Capture3 Capture4 Module 2000 Microchip Technology Inc. ...
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... RG3/AN0/V + REF RG4/CAP3 RG5/PWM3 RG6/RX2/DT2 RG7/TX2/CK2 PORTH Timer0 RH0 RH1 RH2 RH3 RH4/AN12 RH5/AN13 Timer1 RH6/AN14 RH7/AN15 Interrupt Module 2000 Microchip Technology Inc. IR<16> WREG<8> BITOP mult ALU PRODH PRODL Shifter BSR <7:4> <7:0> Read/Write Instruction Decode RAM Decode for Address ...
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... RB6 can also be used as the master/slave clock for the SPI I/O ST RB7 can also be used as the data output for the SPI. I/O = Input/Output; TTL = TTL input Schmitt Trigger input Description /4) of OSC1 and OSC 2 C bus bus. 2000 Microchip Technology Inc. ...
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... RF7/AN11 Legend Input only Output only Power; — = Not Used; Note 1: The output is only available by the peripheral operation. 2: Open drain input/output pin. Pin forced to input upon any device RESET. 2000 Microchip Technology Inc. PIC17C76X PLCC QFP I/O/P Buffer No. No. Type Type PORTC is a bi-directional I/O Port ...
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... Ground reference for A/D converter. This pin MUST be at the same potential Positive supply for A/D converter. This pin MUST be at the same potential 22, — No Connect. Leave these pins unconnected. 43, 64 I/O = Input/Output; TTL = TTL input Schmitt Trigger input Description 2000 Microchip Technology Inc. ...
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... The main difference between the LF and XT modes is the gain of the internal inverter of the oscillator circuit, which allows the different frequency ranges. For more details on the device configuration bits, see Section 17.0. 2000 Microchip Technology Inc. PIC17C7XX 4.1.2 CRYSTAL OSCILLATOR/CERAMIC RESONATORS modes, a crystal or ceramic resonator is con- nected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 4-2) ...
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... MHz 15-47 pF 15- MHz 15-47 pF 15-47 pF (1) 15-47 pF 15-47 pF (1) 10-47 pF 10-47 pF may be S Epson C-001R32.768K-A 20 PPM ECS-10-13-1 50 PPM ECS-20-20-1 50 PPM ECS-40-20-1 50 PPM ECS ECS-80-S-4 50 PPM ECS-80-18-1 ECS-160-20-1 50 PPM CTS CTS25M 50 PPM CRYSTEK HF-2 50 PPM 2000 Microchip Technology Inc. ...
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... The 4.7 k resistor provides the negative feedback for stability. The 10 k ter biases the 74AS04 in the linear region. This could be used for external oscillator designs. 2000 Microchip Technology Inc. FIGURE 4-5: + 74AS04 10k 20 pF Figure 4-6 shows a series resonant oscillator circuit ...
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... The time required for the RC to start oscil- lating depends on many factors. These include: • Resistor value used • Capacitor value used • Device V rise time DD • System temperature RC OSCILLATOR MODE PIC17CXXX Internal OSC1 Clock OSC2/CLKOUT /4 OSC 2000 Microchip Technology Inc. ...
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... Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetched instruc- tion is “flushed” from the pipeline, while the new instruction is being fetched and then executed. 2000 Microchip Technology Inc. 4.3 Instruction Flow/Pipelining An “ ...
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... PIC17C7XX NOTES: DS30289B-page 22 2000 Microchip Technology Inc. ...
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... On-chip 10-bit Ripple Counter RC OSC† † This RC oscillator is shared with the WDT when not in a power-up sequence. 2000 Microchip Technology Inc. PIC17C7XX When the device enters the “RESET state”, the Data Direction registers (DDR) are forced set, which will make the I/O hi-impedance inputs ...
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... OSC lation level detectable by the Oscillator Start-up Timer (OST 1024T OST OSC and MCLR are DD ) delay whenever the PWRT OSC OSCILLATOR START-UP TIME (LOW FREQUENCY) POR or BOR Trip Point T 1 OSC T OST T PWRT . 2000 Microchip Technology Inc. ...
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... The Program Counter = 0; that is, the device branches to the RESET vector and places SFRs in WDT Reset states. This is different from the mid-range devices. 4: When BODEN is enabled, else the BOR status bit is unknown. 2000 Microchip Technology Inc. If the device voltage is not within electrical specification at the end of a time-out, the MCLR/V held low until the voltage is within the device specifica- tion ...
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... PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 5-7: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS30289B-page 26 PWRT timer time-out, may be OST T PWRT T OST T PWRT T OST ) DD Minimum V Operating Voltage PWRT T OST ) 2000 Microchip Technology Inc. ...
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... This is the value that will be in the port output latch. 5: When the device is configured for Microprocessor or Extended Microcontroller mode, the operation of this port does not rely on these registers any device RESET, these pins are configured as inputs. 2000 Microchip Technology Inc. Power-on Reset MCLR Reset Brown-out Reset ...
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... Microchip Technology Inc. ...
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... This is the value that will be in the port output latch. 5: When the device is configured for Microprocessor or Extended Microcontroller mode, the operation of this port does not rely on these registers any device RESET, these pins are configured as inputs. 2000 Microchip Technology Inc. Power-on Reset MCLR Reset Brown-out Reset ...
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... Wake-up from SLEEP through Interrupt uuu- ---- uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu ---- ---- uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 2000 Microchip Technology Inc. ...
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... BROWN-OUT SITUATIONS V DD Internal RESET V DD Internal RESET V DD Internal RESET 2000 Microchip Technology Inc. that may be implemented. Each needs to be evaluated to determine if they match the requirements of the application FIGURE 5- 33k please (typically 4.0 V, This circuit will activate RESET when V (Vz + 0.7V) where Vz = Zener voltage. ...
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... PIC17C7XX NOTES: DS30289B-page 32 2000 Microchip Technology Inc. ...
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... CA3IE TX2IF TX2IE RC2IF RC2IE 2000 Microchip Technology Inc. PIC17C7XX When an interrupt is responded to, the GLINTD bit is automatically set to disable any further interrupts, the return address is pushed onto the stack and the PC is loaded with the interrupt vector address. There are four interrupt vectors ...
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... Prior to disabling any of the INTSTA enable bits, the GLINTD bit should be set (disabled). R/W-0 R/W-0 R/W-0 R/W-0 T0IF INTF PEIE T0CKIE W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-0 R/W-0 T0IE INTE bit Bit is unknown 2000 Microchip Technology Inc. ...
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... Disable USART1 Transmit buffer empty interrupt bit 0 RC1IE: USART1 Receive Interrupt Enable bit 1 = Enable USART1 Receive buffer full interrupt 0 = Disable USART1 Receive buffer full interrupt Legend Readable bit - n = Value at POR Reset 2000 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 TMR2IE TMR1IE CA2IE W = Writable bit U = Unimplemented bit, read as ‘ ...
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... Legend Readable bit - n = Value at POR Reset DS30289B-page 36 R/W-0 U-0 R/W-0 R/W-0 ADIE CA4IE CA3IE — Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-0 R/W-0 TX2IE RC2IE bit Bit is unknown 2000 Microchip Technology Inc. ...
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... USART1 Receive buffer is full 0 = USART1 Receive buffer is empty Legend Readable bit - n = Value at POR Reset 2000 Microchip Technology Inc. Note: These bits will be set by the specified condi- tion, even if the corresponding interrupt enable bit is cleared (interrupt disabled), or the GLINTD bit is set (all interrupts disabled). ...
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... Value at POR Reset DS30289B-page 38 R/W-0 U-0 R/W-0 R/W-0 ADIF — CA4IF CA3IF W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R-1 R-0 TX2IF RC2IF bit Master mode x = Bit is unknown 2000 Microchip Technology Inc. ...
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... GLINTD bit. 2: Before disabling any of the INTSTA enable bits, the GLINTD bit should be set (disabled). 2000 Microchip Technology Inc. 6.5 RA0/INT Interrupt The external interrupt on the RA0/INT pin is edge trig- gered. Either the rising edge if the INTEDG bit (T0STA< ...
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... PIC17C7XX FIGURE 6-2: INT PIN/T0CKI PIN INTERRUPT TIMING DS30289B-page 40 2000 Microchip Technology Inc. ...
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... UNBANK3, WREG MOVFP UNBANK2, BSR MOVFP UNBANK1, ALUSTA ; RETFIE 2000 Microchip Technology Inc. ; Address for 1st location to save ; Address for 2nd location to save ; Address for 3rd location to save ; Address for 4th location to save ; Address for 5th location to save ; (Label Not used in program) ...
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... Restore FSR value for other values ; ; Pop PCLATH value ; Pop WREG value ; FSR0 does not change ; Pop ALUSTA value ; Restore FSR value for other values ; ; Save the FSR for BSR values ; ; No Status bits are affected ; Return from interrupt (enable interrupts) 2000 Microchip Technology Inc. ...
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... Test Memory and Boot Memory are not required for normal operation of the device. Care should be taken to ensure that no unintended branches occur to these areas. 2000 Microchip Technology Inc. PIC17C7XX FIGURE 7-1: PROGRAM MEMORY MAP AND STACK PC< ...
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... FFFFh OFF-CHIP ON-CHIP 00h 120h 120h 1FFh FFh 1FFh ON-CHIP 0000h On-chip Program Memory 3FFFh 4000h Config. Bits FE00h Test Memory Boot ROM FFFFh OFF-CHIP ON-CHIP 00h 120h 320h 320h 220h FFh 1FFh 3FFh 3FFh 2FFh ON-CHIP 2000 Microchip Technology Inc. ...
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... Note 1: Use of I/O pins is only required for paged memory. 2: This signal is unused for ROM and EPROM devices. 3: 16-bit wide devices are now common and could be used instead of 8-bit wide devices. 2000 Microchip Technology Inc. In Extended Microcontroller mode, when the device is executing out of internal memory, the control signals will continue to be active ...
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... The peripheral registers are in the banked portion of memory, while the core registers are in the unbanked region. To facilitate switching between the peripheral banks, the MOVLB bank instruction has been provided. 2000 Microchip Technology Inc. ...
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... The upper nibble of the BSR specifies this bank. All other GPRs ignore the Bank Select Register (BSR) bits. 3: RAM bank 3 is not implemented on the PIC17C752 and the PIC17C762. Reading any unimplemented reg- ister reads ‘0’s. 4: Bank 8 is only implemented on the PIC17C76X devices. 2000 Microchip Technology Inc. (1) (1) (1) (1) ...
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... RC1/AD1 RC0/AD0 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 RD1/AD9 RD0/AD8 xxxx xxxx uuuu uuuu ---- 1111 ---- 1111 RE1/OE RE0/ALE ---- xxxx ---- uuuu TX1IF RC1IF x000 0010 u000 0010 TX1IE RC1IE 0000 0000 0000 0000 2000 Microchip Technology Inc. ...
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... This is the value that will be in the port output latch. 5: When the device is configured for Microprocessor or Extended Microcontroller mode, the operation of this port does not rely on these registers any device RESET, these pins are configured as inputs. 2000 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 — ...
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... RH1 RH0 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 RJ1 RJ0 xxxx xxxx uuuu uuuu — — ---- ---- ---- ---- — — ---- ---- ---- ---- — — ---- ---- ---- ---- — — ---- ---- ---- ---- xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 2000 Microchip Technology Inc. ...
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... For borrow, the polarity is reversed. Legend Readable bit - n = Value at POR Reset 2000 Microchip Technology Inc recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions be used to alter the ALUSTA register, because these instructions do not affect any status bits. To see how other instructions affect the sta- tus bits, see the “ ...
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... BODEN bit in the Configuration word is programmed). R-1 R/W-1 R-1 STKAV GLINTD Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R-1 R/W-0 R/W-1 PD POR BOR bit Bit is unknown 2000 Microchip Technology Inc. ...
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... These bits select the prescale value for Timer0. T0PS3:T0PS0 0000 0001 0010 0011 0100 0101 0110 0111 1xxx bit 0 Unimplemented: Read as ’0’ Legend Readable bit - n = Value at POR Reset 2000 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 T0CS T0PS3 T0PS2 ) CY Prescale Value 1:1 1:2 1:4 1:8 1:16 1:32 ...
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... BSR. If file INDF0 (or INDF1) itself is read indirectly via an FSR, all '0's are read (Zero bit is set). Similarly, if INDF0 (or INDF1) is written to indirectly, the operation will be equivalent to a NOP, and the status bits are not affected. 2000 Microchip Technology Inc. RAM FSR ...
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... FSR0 = END_RAM+1? GOTO LP ; NO, clear next : ; YES, All RAM cleared 2000 Microchip Technology Inc. PIC17C7XX 7.5 Table Pointer (TBLPTRL and TBLPTRH) File registers TBLPTRL and TBLPTRH form a 16-bit pointer to address the 64K program memory space. The table pointer is used by instructions TABLWT and TABLRD ...
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... The following PC related operations do not change PCLATH: a) LCALL, RETLW, and RETFIE instructions. b) Interrupt vector is forced onto the PC. c) Read-modify-write instructions on PCL 0 (e.g. BSF PCL). PCL ALU or destination PCL data bus ALU data bus PCL PCH PC<15:0> PC<12:0> PCLATH<4:0> 2000 Microchip Technology Inc. ...
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... For the GPRs, Bank 3 is unimplemented on the PIC17C752 and the PIC17C762. Selection of an unimplemented bank is not recommended. 3: SFR Bank 8 is only implemented on the PIC17C76X. 2000 Microchip Technology Inc. bank in order to address all peripherals related to a sin- gle task. To assist this, a MOVLB bank instruction has been included in the instruction set ...
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... PIC17C7XX NOTES: DS30289B-page 58 2000 Microchip Technology Inc. ...
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... TLWT 1,f TLWT 0,f Data Memory Program Memory f 1 Step 1: 8-bit value from register ’f’, loaded into the high or low byte in TABLAT (16-bit). 2000 Microchip Technology Inc. PIC17C7XX FIGURE 8-2: TABLWT INSTRUCTION OPERATION TABLE POINTER TBLPTRH TBLPTRL TABLE LATCH (16-bit) ...
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... Prog-Mem (TBLPTR) 2 Step 1: 8-bit value from TABLAT (16-bit) high or low byte, loaded into register ’f’. 2: 16-bit value at Program Memory (TBLPTR), loaded into TABLAT register “i” then TBLPTR = TBLPTR + 1, If “i” then TBLPTR is unchanged. 2000 Microchip Technology Inc. 3 ...
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... Peripheral 2000 Microchip Technology Inc. 8.1.1 TERMINATING LONG WRITES An interrupt source or RESET are the only events that terminate a long write operation. Terminating the long write from an interrupt source requires that the interrupt enable and flag bits are set. The GLINTD bit only enables the vectoring to the interrupt address ...
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... PC+1 TBL Data out INST (PC+1) TABLWT cycle1 TABLWT cycle2 Data write cycle Flag bit, do table write. ; Clear WDT ; address ; ; ; Load HI byte ; in TABLATH ; Load LO byte ; in TABLATL ; and write to ; program memory ; (Ext. SRAM) PC+2 INST (PC+2) INST (PC+1) 2000 Microchip Technology Inc. ...
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... Instruction TABLWT1 TABLWT2 Fetched Instruction INST (PC-1) TABLWT1 cycle1 TABLWT1 cycle2 TABLWT2 cycle1 TABLWT2 cycle2 Executed ALE OE WR 2000 Microchip Technology Inc. TBL1 Data out 1 PC+2 TBL2 INST (PC+2) Data write cycle Data write cycle PIC17C7XX Data out 2 PC+3 INST (PC+3) ...
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... Dummy read, ; Updates TABLATH ; Increments TBLPTR 1, INDF0 ; Read HI byte ; of TABLATH 0, 1, INDF0 ; Read LO byte ; of TABLATL and ; Update TABLATH ; Increment TBLPTR Data in PC+2 INST (PC+2) INST (PC+1) TBL2 Data in 2 PC+3 INST (PC+3) INST (PC+2) Data read cycle 2000 Microchip Technology Inc. ...
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... TLWT and then the TABLWT instructions. FIGURE 8-9: ACCESSING EXTERNAL MEMORY WITH TABLRD AND TABLWT INSTRUCTIONS TABLPTR TABLATH (for Table Reads) TABLATH (for Table Writes) 2000 Microchip Technology Inc. PIC17C7XX Program Memory (In External Memory Space) TABLRD TABLWT DS30289B-page 65 ...
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... PIC17C7XX NOTES: DS30289B-page 66 2000 Microchip Technology Inc. ...
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... Without hardware multiply Hardware multiply signed Without hardware multiply Hardware multiply 2000 Microchip Technology Inc. PIC17C7XX Example 9-2 shows the sequence signed multiply. To account for the sign bits of the arguments, each argument’s most significant bit (MSb) is tested and the appropriate subtractions are done. ...
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... PRODH, RES3 ; PRODL, RES2 ; ARG1L, WREG ARG2H ; ARG1L * ARG2H -> ; PRODH:PRODL PRODL, WREG ; RES1 Add cross PRODH, WREG ; products RES2 WREG RES3 ARG1H, WREG ; ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL, WREG ; RES1 Add cross PRODH, WREG ; products RES2 WREG RES3 2000 Microchip Technology Inc. ...
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... MULTIPLICATION ALGORITHM RES3:RES0 = ARG1H:ARG1L ARG2H:ARG2L 16 = (ARG1H ARG2H (ARG1H ARG2L (ARG1L ARG2H 2 ) (ARG1L ARG2L) (-1 ARG2H<7> ARG1H:ARG1L 2 (-1 ARG1H<7> ARG2H:ARG2L 2 2000 Microchip Technology Inc. EXAMPLE 9-4: MOVFP ARG1L, WREG MULWF ARG2L MOVPF PRODH, RES1 ; MOVPF PRODL, RES0 ; ; MOVFP ARG1H, WREG MULWF ARG2H MOVPF PRODH, RES3 ...
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... PIC17C7XX NOTES: DS30289B-page 70 2000 Microchip Technology Inc. ...
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... PWM Modules • USART/SCI Modules • SSP Module • A/D Module • External Interrupt pin 2000 Microchip Technology Inc. PIC17C7XX When some of these peripheral modules are turned on, the port pin will automatically configure to the alternate function. The modules that do this are: • ...
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... RA0 AND RA1 BLOCK DIAGRAM Note: Input pins have protection diodes to V FIGURE 10-2: RA2 BLOCK DIAGRAM Peripheral Data Mode Enable Note: I/O pin has protection diodes to V 2000 Microchip Technology Inc. Data Bus RD_PORTA (Q2) and Data Bus RD_PORTA (Q2) WR_PORTA (Q4) SCL Out . SS ...
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... Bank 0 TXSTA1 CSRC TX9 Legend unknown unchanged unimplemented, reads as '0'. Shaded cells are not used by PORTA. Note 1: On any device RESET, these pins are configured as inputs. 2000 Microchip Technology Inc. FIGURE 10-4: Data Bus RD_PORTA (Q2) WR_PORTA OE = SPEN,SYNC,TXEN, CREN, SREN for RA4 ...
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... On a device RESET, the RBIF bit is inde- terminate, since the value in the latch may be different than the pin. Port Input Latch D Port Q Data CK and Peripheral Data In RBPU (PORTA<7>) Match Signal from other port pins RBIF Data Bus RD_DDRB (Q2) RD_PORTB (Q2 WR_DDRB (Q4) CK WR_PORTB (Q4) 2000 Microchip Technology Inc. ...
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... MOVLB instruction to load the BSR register for bank selection. FIGURE 10-6: BLOCK DIAGRAM OF RB3:RB2 PORT PINS Weak Pull-up OE Note: I/O pins have protection diodes to V and V DD 2000 Microchip Technology Inc. EXAMPLE 10-2: MOVLB 0 CLRF PORTB, F MOVLW 0xCF MOVWF DDRB ...
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... RBIF Data Bus RD_DDRB (Q2) RD_PORTB (Q2 WR_DDRB (Q4) CK WR_PORTB (Q4) SPI Output SPI Output Enable Peripheral Data In (PORTA<7>) RBPU Match Signal from other port pins RBIF Data Bus RD_DDRB (Q2) RD_PORTB (Q2 WR_DDRB (Q4 Output Disable WR_PORTB (Q4) SPI Output SPI Output Enable 2000 Microchip Technology Inc. ...
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... TCON2 CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON Legend unknown unchanged unimplemented, read as ’0’ value depends on condition. Shaded cells are not used by PORTB. 2000 Microchip Technology Inc. Function Input/output or the Capture1 input pin. Software programmable weak pull-up and interrupt-on-change features. Input/output or the Capture2 input pin. Software programmable weak pull-up and interrupt-on-change features ...
Page 78
... Initialize PORTC data ; latches before setting ; the data direction reg ; Value used to initialize ; data direction ; Set RC<3:0> as inputs ; RC<5:4> as outputs ; RC<7:6> as inputs To D_Bus IR INSTRUCTION READ Data Bus RD_PORTC WR_PORTC RD_DDRC WR_DDRC EX_EN DATA/ADDR_OUT System Bus Control DRV_SYS 2000 Microchip Technology Inc. ...
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... RC6/ AD7 AD6 10h, Bank 1 DDRC Data Direction Register for PORTC Legend unknown unchanged 2000 Microchip Technology Inc. Function Input/output or system bus address/data pin. Input/output or system bus address/data pin. Input/output or system bus address/data pin. Input/output or system bus address/data pin. Input/output or system bus address/data pin. ...
Page 80
... Initialize PORTD data ; latches before setting ; the data direction reg ; Value used to initialize ; data direction ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs To D_Bus IR INSTRUCTION READ Data Bus RD_PORTD WR_PORTD RD_DDRD WR_DDRD EX_EN DATA/ADDR_OUT System Bus Control DRV_SYS 2000 Microchip Technology Inc. ...
Page 81
... RD6/ AD15 AD14 12h, Bank 1 DDRD Data Direction Register for PORTD Legend unknown unchanged 2000 Microchip Technology Inc. Function Input/output or system bus address/data pin. Input/output or system bus address/data pin. Input/output or system bus address/data pin. Input/output or system bus address/data pin. Input/output or system bus address/data pin. ...
Page 82
... Initialize PORTE data ; latches before setting ; the data direction ; register ; Value used to initialize ; data direction ; Set RE<1:0> as inputs ; RE<3:2> as outputs ; RE<7:4> are always ; read as ’0’ Data Bus RD_PORTE WR_PORTE RD_DDRE WR_DDRE EX_EN CNTL System Bus Control DRV_SYS 2000 Microchip Technology Inc. ...
Page 83
... Data Direction Register for PORTE 14h, Bank 7 CA4L Capture4 Low Byte 15h, Bank 7 CA4H Capture4 High Byte 16h, Bank 7 TCON3 — CA4OVF Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by PORTE. 2000 Microchip Technology Inc Port CK Data ...
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... MOVWF DDRF other pads To other pads and INITIALIZING PORTF ; Select Bank 5 ; Configure PORTF as ; Digital ; Initialize PORTF data ; latches before ; the data direction ; register ; Value used to init ; data direction ; Set RF<1:0> as inputs ; RF<7:2> as outputs I/O pin Input Buffer 2000 Microchip Technology Inc. ...
Page 85
... RF7/ RF6/ AN11 AN10 15h, Bank 5 ADCON1 ADCS1 ADCS0 Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by PORTF. 2000 Microchip Technology Inc. Function Input/output or analog input 4. Input/output or analog input 5. Input/output or analog input 6. Input/output or analog input 7. Input/output or analog input 8. ...
Page 86
... MOVWF DDRG other pads To other pads and INITIALIZING PORTG ; Select Bank 5 ; Configure PORTG as ; digital ; Initialize PORTG data ; latches before ; the data direction ; register ; Value used to init ; data direction ; Set RG<1:0> as inputs ; RG<7:2> as outputs I/O pin Input Buffer 2000 Microchip Technology Inc. ...
Page 87
... FIGURE 10-15: RG4 BLOCK DIAGRAM Note: I/O pins have protection diodes to V FIGURE 10-16: RG7:RG5 BLOCK DIAGRAM Note: I/O pins have protection diodes to V 2000 Microchip Technology Inc and Port Data and PIC17C7XX Peripheral Data In Data Bus RD_PORTG WR_PORTG RD_DDRG WR_DDRG ...
Page 88
... Bit 1 RG5/ RG4/ RG3/ RG2/ RG1/ PWM3 CAP3 AN0 AN1 AN2 ADFM — PCFG3 PCFG2 PCFG1 Value on Bit 0 POR, MCLR, WDT BOR 1111 1111 1111 1111 RG0/ xxxx 0000 uuuu 0000 AN3 PCFG0 000- 0000 000- 0000 2000 Microchip Technology Inc. ...
Page 89
... PORTH CK Q Data Latch DDRH CK Q DDRH Latch RD DDRH RD PORT PCFG3:PCFG0 V AIN CHS3:CHS0 Note: I/O pins have protection diodes to V 2000 Microchip Technology Inc. EXAMPLE 10-8: MOVLB 8 MOVLW 0x0E MOVPF ADCON1 CLRF PORTH, F MOVLW 0x03 MOVWF DDRH other pads To other pads and V ...
Page 90
... RH4/ RH3 RH2 RH1 AN13 AN12 ADFM — PCFG3 PCFG2 PCFG1 Data Bus RD_PORTH WR_PORTH RD_DDRH WR_DDRH Value on Bit 0 POR, MCLR, WDT BOR 1111 1111 1111 1111 RH0 0000 xxxx 0000 uuuu PCFG0 000- 0000 000- 0000 2000 Microchip Technology Inc. ...
Page 91
... PORTJ will write to the respective port latch. PORTJ is a general purpose I/O port. FIGURE 10-19: PORTJ BLOCK DIAGRAM Note: I/O pins have protection diodes to V 2000 Microchip Technology Inc. EXAMPLE 10-9: MOVLB 8 CLRF PORTJ, F MOVLW 0xCF MOVWF DDRJ ...
Page 92
... Legend unknown unchanged DS30289B-page 92 Function Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RJ5 RJ4 RJ3 RJ2 RJ1 Value on, MCLR, Bit 0 POR, WDT BOR 1111 1111 1111 1111 RJ0 xxxx xxxx uuuu uuuu 2000 Microchip Technology Inc. ...
Page 93
... BTG, etc port, the value of the port pins is read, the desired operation is performed with this value and the value is then written to the port latch. Example 10-10 shows the possible effect of two sequential read-modify-write instructions on an I/O port. 2000 Microchip Technology Inc. PIC17C7XX EXAMPLE 10-10: READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT ...
Page 94
... PORTx, PINy pin. Note: This example shows a write to PORTB, followed by a read from PORTB. Note that: data setup time = (0.25T - where T = instruction cycle propagation delay PD Therefore, at higher clock frequencies, a write followed by a read may be problematic. BSF PORTx, PINz 2000 Microchip Technology Inc. ...
Page 95
... When the TMR2:TMR1 value rolls over from the period match value to 0h, the TMR1IF flag is set and an interrupt will be generated, if enabled. 2000 Microchip Technology Inc. PIC17C7XX 11.3 Timer2 Overview The Timer2 module is an 8-bit timer/counter with an 8- bit period register (PR2) ...
Page 96
... PIC17C7XX NOTES: DS30289B-page 96 2000 Microchip Technology Inc. ...
Page 97
... These bits select the prescale value for TMR0. T0PS3:T0PS0 Prescale Value 0000 0001 0010 0011 0100 0101 0110 0111 1xxx bit 0 Unimplemented: Read as ’0’ Legend Readable bit - n = Value at POR Reset 2000 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 T0CS T0PS3 T0PS2 ) CY 1:1 1:2 1:4 1:8 1:16 1:32 1:64 ...
Page 98
... Prescaler (8 Stage Synchronization Async Ripple PSOUT Counter T0PS3:T0PS0 (T0STA<4:1>) (Note and 7T . Thus, for example, mea- OSC ( 121 MHz). OSC Interrupt-on-Overflow sets T0IF (INTSTA<5>) TMR0H<8> TMR0L<8> (Note 3) (Note 2000 Microchip Technology Inc. ...
Page 99
... TMR0L Fetch MOVFP W,TMR0L Instruction Executed TMR0H 2000 Microchip Technology Inc. 12.3.2 WRITING A 16-BIT VALUE TO TMR0 Since writing to either TMR0L or TMR0H will effectively inhibit increment of that half of the TMR0 in the next cycle (following write), but not inhibit increment of the other half, the user must write to TMR0L first and TMR0H second, in two consecutive instructions, as shown in Example 12-2 ...
Page 100
... TMR0L,W TMR0L,W Read TMR0L Read TMR0L Value on Bit 1 Bit 0 POR, MCLR, WDT BOR T0PS0 — 0000 000- 0000 000- POR BOR --11 11qq --11 qquu T0IE INTE 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 2000 Microchip Technology Inc. ...
Page 101
... TMR1 increments off the falling edge of the RB4/TCLK12 pin 0 = TMR1 increments off the internal clock Legend Readable bit - n = Value at POR Reset 2000 Microchip Technology Inc. Six other registers comprise the Capture2, Capture3, and Capture4 registers (CA2H:CA2L, CA3H:CA3L, and CA4H:CA4L). Figure 13-1, Figure 13-2 and Figure 13-3 are the con- ...
Page 102
... R = Readable bit - n = Value at POR Reset DS30289B-page 102 R/W-0 R/W-0 R/W-0 PWM2ON PWM1ON CA1/PR3 TMR3ON W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-0 R/W-0 R/W-0 TMR2ON TMR1ON bit Bit is unknown 2000 Microchip Technology Inc. ...
Page 103
... PWM3ON: PWM3 On bit 1 = PWM3 is enabled (the RG5/PWM3 pin ignores the state of the DDRG<5> bit PWM3 is disabled (the RG5/PWM3 pin uses the state of the DDRG<5> bit for data direction) Legend Readable bit - n = Value at POR Reset 2000 Microchip Technology Inc. R-0 R/W-0 R/W-0 CA3OVF CA4ED1 ...
Page 104
... TCLK12 to the time TMR1 or TMR2 is actually incre- mented. For the external clock input timing require- ments, see the Electrical Specification section. RESET TMR1 TMR1ON Comparator<8> Comparator x8 (TCON2<0>) Equal PR1 RESET TMR2 TMR2ON Comparator<8> Comparator x8 (TCON2<1>) Equal PR2 Set TMR1IF (PIR1<4>) Set TMR2IF (PIR1<5>) 2000 Microchip Technology Inc. ...
Page 105
... OSC TMR1CS (TCON1<0>) Set Interrupt TMR1IF (PIR1<4>) 2000 Microchip Technology Inc. 13.1.2.1 When TMR1CS is set, the 16-bit TMR2:TMR1 incre- ments on the falling edge of clock input TCLK12. The input on the RB4/TCLK12 pin is sampled and synchro- nized by the internal phase clocks twice every instruc- tion cycle ...
Page 106
... DC2 xxxx xxxx uuuu uuuu DC2 xxxx xxxx uuuu uuuu DC2 xxxx xxxx uuuu uuuu 2000 Microchip Technology Inc. ...
Page 107
... In this example, PWM period = 50. Old duty cycle is 30. New duty cycle value is 10. 2000 Microchip Technology Inc. The user needs to set the PWM1ON bit (TCON2<4>) to enable the PWM1 output. When the PWM1ON bit is ...
Page 108
... These flags must be cleared in software. value from PW1DCH, PW1DCL, PW2DCH, PWM FREQUENCY vs. RESOLUTION AT 33 MHz Frequency (kHz) 32.2 64.5 90.66 128.9 515.6 0xFF 0x7F 0x5A 0x3F 0x0F 9-bit 8.5-bit 8-bit 6-bit 8-bit 7-bit 6.5-bit 6-bit 4-bit 2000 Microchip Technology Inc. ...
Page 109
... DC9 DC8 Legend unknown unchanged unimplemented, read as '0 value depends on conditions. Shaded cells are not used by PWM Module. 2000 Microchip Technology Inc. 13.1.3.4 Maximum Resolution/Frequency for External Clock Input The use of an external clock for the PWM time base (Timer1 or Timer2) limits the PWM output to a maxi- mum resolution of 8-bits. The PWxDCL< ...
Page 110
... TMR3IF must be cleared in software. PR3H/CA1H PR3L/CA1L Comparator<8> Comparator x16 TMR3H TMR3L Capture2 Enable CA2H CA2L Set CA2IF (PIR1<3>) Capture3 Enable CA3H CA3L Set CA3IF (PIR2<2>) Capture4 Enable CA4H CA4L Set CA4IF (PIR2<3>) Set TMR3IF (PIR1<6>) Equal Reset 2000 Microchip Technology Inc. ...
Page 111
... CAxIE. If the CAPx pin is used as an output pin, the user can activate a capture by writing to the port pin. This may be useful during development phase to emulate a capture interrupt. 2000 Microchip Technology Inc. PIC17C7XX The input on the capture pin CAPx is synchronized internally to internal phase clocks. This imposes certain restrictions on the input waveform (see the Electrical Specification section for timing) ...
Page 112
... Section 13.2.1 for the operation of capture. TMR3H Capture1 Enable Set CA1IF (PIR1<2>) PR3H/CA1H PR3L/CA1L Capture2 Enable Set CA2IF (PIR1<3>) CA2H CA2L Capture3 Enable Set CA3IF (PIR2<2>) CA3H CA3L Capture4 Enable Set CA4IF (PIR2<3>) CA4H CA4L 2000 Microchip Technology Inc. Set TMR3IF (PIR1<6>) TMR3L ...
Page 113
... Legend unknown unchanged unimplemented, read as '0 value depends on condition. Shaded cells are not used by Capture. 2000 Microchip Technology Inc. order) of the Capture register, the master overflow bit is transferred to the slave overflow bit (CAxOVF) and then the master bit is reset. The user can then read TCONx to determine the value of CAxOVF ...
Page 114
... TMR3 ; read high TMR3 ; return 35h A8h MOVWF MOVFP MOVFP TMRx TMRx,W TMRx,W Write to TMRx Read TMRx Read TMRx indicates a sampling point. to timer increment is between 2Tosc and 6Tosc. A9h 00h ’A9h’ 2000 Microchip Technology Inc. ...
Page 115
... Read TMR1 Write TMR1 Read TMR1 TMR1 04h 05h 03h PR1 TMR1ON WR_TMR1 WR_TCON2 TMR1IF RD_TMR1 TMR1 Reads 03h 2000 Microchip Technology Inc. BSF BCF NOP MOVLB 3 NOP TCON2, 0 TCON2, 0 Start TMR1 Stop TMR1 04h 05h 06h TMR1 Reads 04h PIC17C7XX ...
Page 116
... PIC17C7XX NOTES: DS30289B-page 116 2000 Microchip Technology Inc. ...
Page 117
... TRMT: Transmit Shift Register (TSR) Empty bit 1 = TSR empty 0 = TSR full bit 0 TX9D: 9th bit of Transmit Data (can be used to calculate the parity in software) Legend Readable bit - n = Value at POR Reset 2000 Microchip Technology Inc. TABLE 14-1: USART MODULE GENERIC NAMES Generic Name USART1 Name USART2 Name RCSTA TXSTA ...
Page 118
... TXEN • SREN • CREN • CSRC R/W-0 R/W-0 U-0 SREN CREN — FERR W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R-0 R-0 R-x OERR RX9D bit Bit is unknown 2000 Microchip Technology Inc. ...
Page 119
... FIGURE 14-1: USART TRANSMIT Sync/Async CK/TX DT FIGURE 14-2: USART RECEIVE OSC 4 BRG Buffer Logic CK SPEN Buffer Logic RX 2000 Microchip Technology Inc. BRG Sync/Async TSR Clock Start Stop Load 8 Bit Count TXREG TXSTA<0> Data Bus Master/Slave Sync/Async Sync Bit Count 16 START Detect ...
Page 120
... RATE ERROR / ( 1)) OSC 25 Desired Baud Rate Value on Bit 1 Bit 0 POR, MCLR, WDT BOR RX9D 0000 -00x 0000 -00u TX9D 0000 --1x 0000 --1u 0000 0000 0000 0000 RX9D 0000 -00x 0000 -00u TX9D 0000 --1x 0000 --1u 0000 0000 0000 0000 2000 Microchip Technology Inc. ...
Page 121
... NA — HIGH 894.9 — LOW 3.496 — 2000 Microchip Technology Inc MHz = 20 MHz OSC SPBRG VALUE %ERROR (DECIMAL) KBAUD %ERROR — — NA — — — NA — — — NA — ...
Page 122
... F = 32.768 kHz OSC SPBRG VALUE KBAUD %ERROR (DECIMAL) 0.256 -14. — — NA — — NA — — NA — — NA — — NA — — NA — — NA — — 0.512 — 0 0.002 — 255 2000 Microchip Technology Inc. ...
Page 123
... TXIF bit Word 1 Transmit Shift Reg TRMT bit 2000 Microchip Technology Inc. TRMT is a read only bit which is set when the TSR is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR is empty. Note: The TSR is not mapped in data memory not available to the user ...
Page 124
... TX9D 0000 --1x 0000 --1u 0000 0000 0000 0000 RC2IF 000- 0010 000- 0010 RC2IE 000- 0000 000- 0000 RX9D 0000 -00x 0000 -00u xxxx xxxx uuuu uuuu TX9D 0000 --1x 0000 --1u 0000 0000 0000 0000 2000 Microchip Technology Inc. ...
Page 125
... RX (RX/DT pin) x16 CLK Q2, Q4 CLK 2000 Microchip Technology Inc. ting the receive logic (CREN is set). If the OERR bit is set, transfers from the RSR to RCREG are inhibited essential to clear the OERR bit set. The fram- ing error bit FERR (RCSTA<2>) is set if a STOP bit is not detected ...
Page 126
... TX9D 0000 --1x 0000 --1u 0000 0000 0000 0000 RC2IF 000- 0010 000- 0010 RC2IE 000- 0000 000- 0000 RX9D 0000 -00x 0000 -00u RX0 xxxx xxxx uuuu uuuu TX9D 0000 --1x 0000 --1u 0000 0000 0000 0000 2000 Microchip Technology Inc. ...
Page 127
... TSR is empty transfer to TXREG will result in an immediate transfer to the TSR, resulting in an empty TXREG. Back-to-back transfers are possible. 2000 Microchip Technology Inc. PIC17C7XX Clearing TXEN during a transmission will cause the transmission to be aborted and will reset the transmit- ter ...
Page 128
... TX9D 0000 --1x 0000 --1u 0000 0000 0000 0000 RC2IF 000- 0010 000- 0010 RC2IE 000- 0000 000- 0000 RX9D 0000 -00x 0000 -00u TX0 xxxx xxxx uuuu uuuu TX9D 0000 --1x 0000 --1u 0000 0000 0000 0000 Word 2 bit6 bit7 2000 Microchip Technology Inc. ...
Page 129
... CREN bit RCIF bit Read RCREG Note: Timing diagram demonstrates SYNC Master mode with SREN = 1. 2000 Microchip Technology Inc. Steps to follow when setting up a Synchronous Master Reception: 1. Initialize the SPBRG register for the appropriate baud rate. See Section 14.1 for details. ...
Page 130
... TX9D 0000 --1x 0000 --1u 0000 0000 0000 0000 RC2IF 000- 0010 000- 0010 RC2IE 000- 0000 000- 0000 RX9D 0000 -00x 0000 -00u RX0 xxxx xxxx uuuu uuuu TX9D 0000 --1x 0000 --1u 0000 0000 0000 0000 2000 Microchip Technology Inc. ...
Page 131
... To terminate a transmission, either clear the SPEN bit, or the TXEN bit. This will reset the transmit logic, so that it will be in the proper state when transmit is re- enabled. 2000 Microchip Technology Inc. PIC17C7XX 14.4.2 USART SYNCHRONOUS SLAVE RECEPTION Operation of the Synchronous Master and Slave modes are identical except in the case of the SLEEP mode. Also, SREN is a “ ...
Page 132
... TX9D 0000 --1x 0000 --1u 0000 0000 0000 0000 RC2IF 000- 0010 000- 0010 RC2IE 000- 0000 000- 0000 RX9D 0000 -00x 0000 -00u RX0 xxxx xxxx uuuu uuuu TX9D 0000 --1x 0000 --1u 0000 0000 0000 0000 2000 Microchip Technology Inc. ...
Page 133
... Edge Select 2 Clock Select SSPM3:SSPM0 SMP:CKE 4 2 Edge Select Prescaler SCK 4, 16, 64 Data to TX/RX in SSPSR Data Direction bit 2000 Microchip Technology Inc. FIGURE 15-2: SCL SDA Internal Data Bus FIGURE 15-3: Shift Clock SSPADD<6:0> 7 Baud Rate Generator SCL SDA TMR2 Output ...
Page 134
... Value at POR Reset DS30289B-page 134 R-0 R-0 R-0 D mode only mode only mode only modes Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R-0 R-0 R-0 R bit Bit is unknown 2000 Microchip Technology Inc. ...
Page 135
... C Slave mode, 7-bit address 2 0111 = I C Slave mode, 10-bit address 2 1000 = I C Master mode, clock = F 1xx1 = Reserved 1x1x = Reserved Legend Readable bit - n = Value at POR Reset 2000 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 SSPM2 2 C conditions were not valid for a /4 ...
Page 136
... C module is not in the IDLE mode, this bit may not be set (no spooling) and W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-0 R/W-0 R/W-0 PEN RSEN SEN bit Bit is unknown 2000 Microchip Technology Inc. ...
Page 137
... SCK) • Clock Rate (Master mode only) • Slave Select mode (Slave mode only) Figure 15-4 shows the block diagram of the MSSP module when in SPI mode. 2000 Microchip Technology Inc. FIGURE 15-4: Read SSPBUF reg SDI bit0 ...
Page 138
... Master sends data — Slave sends data • Master sends dummy data — Slave sends data SPI Slave SSPM3:SSPM0 = 010 xb SDO SDI SDI SDO LSb Serial Clock SCK SCK Serial Input Buffer (SSPBUF) Shift Register (SSPSR) MSb LSb PROCESSOR 2 2000 Microchip Technology Inc. ...
Page 139
... SDI (SMP = 1) bit7 Input Sample (SMP = 1) SSPIF SSPSR to SSPBUF 2000 Microchip Technology Inc. Figure 15-6, Figure 15-8 and Figure 15-9, where the MSb is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: • ( OSC CY • ...
Page 140
... SDO pin can be configured as an input. This disables transmissions from the SDO. The SDI can always be left as an input (SDI function), since it cannot create a bus conflict. bit6 bit7 bit7 . DD bit0 bit0 Next Q4 cycle after Q2 2000 Microchip Technology Inc. ...
Page 141
... SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO bit7 SDI (SMP = 0) bit7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF 2000 Microchip Technology Inc. bit6 bit5 bit4 bit2 bit3 bit6 bit2 bit5 bit4 bit3 PIC17C7XX bit1 bit0 bit0 Next Q4 cycle after Q2 bit1 bit0 ...
Page 142
... SSPM3 SSPM2 SSPM1 D R/W UA Bit 0 POR, BOR MCLR, WDT INTE 0000 0000 0000 0000 RC2IF 000- 0010 000- 0010 RC2IE 000- 0000 000- 0000 xxxx xxxx uuuu uuuu SSPM0 0000 0000 0000 0000 BF 0000 0000 0000 0000 2000 Microchip Technology Inc. ...
Page 143
... Clock SSPSR reg SDA MSb LSb Match Detect SSPADD reg START and STOP bit Detect 2000 Microchip Technology Inc. FIGURE 15-11: SSPADD<6:0> 7 Baud Rate Generator SCL SDA Internal Data Bus Two pins are used for data transfer. These are the SCL pin, which is the clock and the SDA pin, which is the data ...
Page 144
... The SCL clock input must have a minimum high and low time for proper operation. The high and low times 2 of the I C specification, as well as the requirement of the MSSP module, are shown in timing parameter #100 and parameter #101 of the Electrical Specifications. 2000 Microchip Technology Inc. ...
Page 145
... Note 1: Shaded cells show the conditions where the user software did not properly clear the overflow condition. 2000 Microchip Technology Inc. 5. Update the SSPADD register with the first (high) byte of Address. This will clear bit UA and release the SCL line. 6. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF ...
Page 146
... SSPBUF is written in software Set bit after writing to SSPBUF (the SSPBUF must be written to before the CKP bit can be set) Not Receiving Data ACK Bus Master Terminates Transfer ACK is not sent. R Transmitting Data Not ACK From SSP Interrupt Service Routine 2000 Microchip Technology Inc. ...
Page 147
... I FIGURE 15-14: C SLAVE-TRANSMITTER (10-BIT ADDRESS) 2000 Microchip Technology Inc. PIC17C7XX DS30289B-page 147 ...
Page 148
... PIC17C7XX 2 FIGURE 15-15 SLAVE-RECEIVER (10-BIT ADDRESS) DS30289B-page 148 2000 Microchip Technology Inc. ...
Page 149
... S SSPIF BF (SSPSTAT<0>) SSPOV (SSPCON1<6>) GCEN (SSPCON2<7>) 2000 Microchip Technology Inc. If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF flag is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the SSPIF flag is set. When the interrupt is serviced, the source for the inter- ...
Page 150
... RC2IF 000- 0000 000- 0000 RC2IE 000- 0000 000- 0000 0000 0000 0000 0000 xxxx xxxx uuuu uuuu SSPM0 0000 0000 0000 0000 SEN 0000 0000 0000 0000 BF 0000 0000 0000 0000 2 C mode. 2000 Microchip Technology Inc. ...
Page 151
... SSP BLOCK DIAGRAM (I SDA SDA In SCL SCL In Bus Collision 2000 Microchip Technology Inc. The following events will cause SSP Interrupt Flag bit, SSPIF set (SSP Interrupt if enabled): • START condition • STOP condition • Data transfer byte transmitted/received • Acknowledge transmit • ...
Page 152
... SSP- BUF. Once the given operation is complete (i.e., trans- mission of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state operation. The baud 2000 Microchip Technology Inc. ...
Page 153
... SCL low (clock arbitration). SCL BRG 03h Value BRG Reload 2000 Microchip Technology Inc. 15.2.8 BAUD RATE GENERATOR Master mode, the reload value for the BRG is located in the lower 7 bits of the SSPADD register (Figure 15-18). When the BRG is loaded with this value, the BRG counts down to 0 and stops until another reload has taken place ...
Page 154
... SSPCON2 is disabled until the START condition is complete. ), the BRG Set S bit (SSPSTAT<3>) SDA = 1, At completion of START bit, SCL = 1 Hardware clears SEN bit and sets SSPIF bit BRG BRG Write to SSPBUF occurs here. 1st Bit T BRG T BRG S 2nd Bit 2000 Microchip Technology Inc. ...
Page 155
... FIGURE 15-21: START CONDITION FLOW CHART Bus Collision Detected, Set BCLIF, Release SCL, Clear SEN No Yes No SCL SCL = 0? Reset BRG 2000 Microchip Technology Inc. SSPEN = 1, SSPCON1<3:0> = 1000 Idle Mode SEN (SSPCON2<0> SDA = 1? SCL = 1? Yes Load BRG with SSPADD<6:0> No BRG SDA = 0? Rollover? ...
Page 156
... SSPCON2 is disabled until the Repeated Start condition is complete. Set S (SSPSTAT<3>) SDA = 1, At completion of START bit, SCL = 1 hardware clear RSEN bit and set SSPIF BRG BRG BRG 1st Bit Write to SSPBUF occurs here T BRG Sr = Repeated Start T BRG 2000 Microchip Technology Inc. ...
Page 157
... FIGURE 15-23: REPEATED START CONDITION FLOW CHART (PAGE 1) B 2000 Microchip Technology Inc. Start Idle Mode, SSPEN = 1, SSPCON1<3:0> = 1000 RSEN = 1 Force SCL = 0 SCL = 0? Yes Release SDA, Load BRG with SSPADD<6:0> BRG Rollover? Yes Release SCL SCL = 1? Yes Bus Collision, No Set BCLIF, ...
Page 158
... DS30289B-page 158 C Yes SDA = 0? SCL = 1? Yes Reset BRG Force SDA = 0, Load BRG with No No SCL = ’0’? Yes Repeated Start Reset BRG condition done, A BRG Rollover? Yes SSPADD<6:0> Set S BRG Rollover? Yes Force SCL = 0, Clear RSEN, Set SSPIF. 2000 Microchip Technology Inc. ...
Page 159
... SSPIF is set, the BF flag is cleared and the baud rate generator is turned off until another write to the SSPBUF takes place, holding SCL low and allowing SDA to float. 2000 Microchip Technology Inc. 15.2.11.1 BF Status Flag In Transmit mode, the BF bit (SSPSTAT<0>) is set when the CPU writes to SSPBUF and is cleared when all 8 bits are shifted out ...
Page 160
... Load BRG with SSPADD<6:0>, start BRG count No BRG Rollover? Yes Force SCL = 1, Stop BRG No SCL = 1? Yes Read SDA and place into ACKSTAT bit (SSPCON2<6>) Load BRG with SSPADD<6:0>, Count High Time No Rollover? Yes Force SCL = 0, Set SSPIF 2000 Microchip Technology Inc. ...
Page 161
... FIGURE 15-26 MASTER MODE TIMING (TRANSMISSION 10-BIT ADDRESS) 2000 Microchip Technology Inc. PIC17C7XX DS30289B-page 161 ...
Page 162
... WCOL Status Flag If the user writes the SSPBUF when a receive is already in progress (i.e., SSPSR is still shifting in a data byte), then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). 2000 Microchip Technology Inc. ...
Page 163
... FIGURE 15-27: MASTER RECEIVER FLOW CHART Move Contents of SSPSR 2000 Microchip Technology Inc. Idle Mode RCEN = 1 Num_Clocks = 0, Release SDA Force SCL=0, Load BRG w/ SSPADD<6:0>, Start Count BRG No Rollover? Yes Release SCL (Clock Arbitration) No SCL = 1? Yes Sample SDA, Shift Data into SSPSR Load BRG with SSPADD< ...
Page 164
... PIC17C7XX 2 FIGURE 15-28 MASTER MODE TIMING (RECEPTION 7-BIT ADDRESS) DS30289B-page 164 2000 Microchip Technology Inc. ...
Page 165
... Set SSPIF at the End of Receive Note one baud rate generator period. BRG 2000 Microchip Technology Inc. 15.2.13.1 WCOL Status Flag If the user writes the SSPBUF when an acknowledge sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn’t ...
Page 166
... Load BRG with SSPADD <6:0>, Start Count. DS30289B-page 166 BRG Yes Rollover? No Yes Force SCL = 0, SCL = 0? Reset BRG Clear ACKEN Set SSPIF No No ACKDT = 1? Yes Yes SDA = 1? No Bus Collision Detected, Set BCLIF, Release SCL, Clear ACKEN 2000 Microchip Technology Inc. ...
Page 167
... SDA asserted low before rising edge of clock to setup STOP condition. Note one baud rate generator period. BRG 2000 Microchip Technology Inc. 15.2.14.1 WCOL Status Flag If the user writes the SSPBUF when a STOP sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn’ ...
Page 168
... Yes DS30289B-page 168 Start BRG No BRG Rollover? Yes Release SDA, Start BRG No BRG Rollover? Yes Bus Collision Detected, No Set BCLIF, P bit Set? Clear PEN Yes SDA going from while SCL = 1 Set SSPIF, STOP Condition done, PEN cleared 2000 Microchip Technology Inc. ...
Page 169
... Release SCL, Slave device holds SCL low. SCL SDA T BRG 2000 Microchip Technology Inc. 15.2.16 SLEEP OPERATION While in SLEEP mode, the I addresses or data and when an address match or com- plete byte transfer occurs, wake the processor from SLEEP (if the SSP interrupt is enabled). ...
Page 170
... STAT register, or the bus is idle and the S and P bits are cleared. Sample SDA. While SCL is high SDA line pulled low by another source. data doesn’t match what is driven by the master. Bus collision has occurred. SDA released by master. Set bus collision interrupt. 2000 Microchip Technology Inc. ...
Page 171
... S bit and SSPIF set because BCLIF SDA = 0, SCL = 1. S SSPIF 2000 Microchip Technology Inc. PIC17C7XX If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 15-37). If, however, a '1' is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count ...
Page 172
... Bus collision occurs, Set BCLIF. SDA = 0, SCL = 1 Set S Set SSPIF BRG T BRG S SCL pulled low after BRG Time-out. Set SEN, enable START sequence if SDA = 1, SCL = 1. SDA = 0, SCL = 1 Set SSPIF. Interrupts cleared in software. ’0’ ’0’ Interrupts cleared in software. 2000 Microchip Technology Inc. ...
Page 173
... Set BCLIF. Release SDA and SCL. RSEN ’0’ S ’0’ SSPIF 2000 Microchip Technology Inc. PIC17C7XX reloaded and begins counting. If SDA goes from high to low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. ...
Page 174
... SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data '0' (Figure 15-40 BRG BRG T BRG SCL goes low before SDA goes high. Set BCLIF. SDA sampled T BRG low after T , BRG Set BCLIF. ’0’ ’0’ T BRG 2000 Microchip Technology Inc. ...
Page 175
... For OL FIGURE 15-42: SAMPLE DEVICE CONFIGURATION FOR I R SDA SCL 2 Note devices with input levels related to V also connected. 2000 Microchip Technology Inc. example, with a supply voltage max = function 42. The desired noise margin of 0.1 V level, limits the maximum value of R are optional and used to improve ESD susceptibility ...
Page 176
... Configure clock for 100KHz // Loop 128 times, 24LC01B is 128x8 // Write data to EEPROM // Poll the 24LC01B for state // Read data from EEPROM into SSPBUF // Loop as long as data not correctly // written to 24LC01B // Increment address // Done writing 128 bytes to 24LC01B, Loop forever 2000 Microchip Technology Inc. ...
Page 177
... IdleI2C(); NotAckI2C(); IdleI2C(); StopI2C(); IdleI2C(); } } } return(SSPBUF); } 2000 Microchip Technology Inc. // Send start bit // Wait for idle condition // Send control byte // Wait for idle condition // If 24LC01B ACKs // Send control byte // Wait for idle condition // If 24LC01B ACKs // Send data // Wait for idle condition ...
Page 178
... Send start bit // Wait for idle condition // Send control byte // Wait for idle condition // Send a restart bit // Wait for idle condition // Send control byte // Wait for idle condition // Wait for idle condition // Send stop bit // Wait for idle condition 2000 Microchip Technology Inc. ...
Page 179
... A/D converter module is shut-off and consumes no operating current Legend Readable bit - n = Value at POR Reset 2000 Microchip Technology Inc. The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. To oper- ate in SLEEP, the A/D clock must be derived from the A/D’ ...
Page 180
... REF REF and AN9 AN8 AN7 Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared R/W-0 R/W-0 R/W-0 PCFG2 PCFG1 PCFG0 bit 0 AN6 AN5 AN4 AN3 AN2 AN1 AN0 Bit is unknown 2000 Microchip Technology Inc. ...
Page 181
... Turn on A/D module (ADCON0) FIGURE 16-1: A/D BLOCK DIAGRAM A/D Converter V (Reference Voltage) V Note 1: These channels are only available on PIC16C76X devices. 2000 Microchip Technology Inc. 2. Configure A/D interrupt (if desired): a) Clear ADIF bit b) Set ADIE bit c) Clear GLINTD bit 3. Wait the required acquisition time. ...
Page 182
... GO bit). When A/D holding capacitor starts to charge. After A/D conversion, or when new A/D channel is selected. DS30289B-page 182 A/D conversion complete, result is loaded in ADRES register. Holding capacitor begins acquiring voltage level on selected channel, ADIF bit is set. 2000 Microchip Technology Inc. ...
Page 183
... The maximum recommended impedance for analog sources This is required to meet the pin leakage specification. 4: After a conversion has completed, a 2.0 T During this time, the holding capacitor is not connected to the selected A/D input channel. 2000 Microchip Technology Inc. To calculate Equation 16-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D) ...
Page 184
... PIN V = threshold voltage T I leakage = leakage current at the pin due to various junctions R = interconnect resistance sampling switch C = sample/hold capacitance (from DAC) HOLD DS30289B-page 184 V DD Sampling Switch leakage V = 0.6V T ± 500 HOLD = DAC capacitance = 120 Sampling Switch ( k ) 2000 Microchip Technology Inc. ...
Page 185
... OSC 64T OSC RC Note: When the device frequency is greater than 1 MHz, the RC A/D conversion clock source is only recommended for SLEEP operation. 2000 Microchip Technology Inc. For correct A/D conversions, the A/D conversion clock (T ) must be selected to ensure a minimum 1 The AD Table 16-1 and Table 16-2 show the resultant T ...
Page 186
... A/D Conversion CYCLES Next Q4: ADRES is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. -) are the device AV and AV . The REF DD SS wait is required before the next AD wait, acquisition AD and a maximum 2000 Microchip Technology Inc. ...
Page 187
... Conversion Delayed = RC? 1 Instruction Cycle No Yes Abort Conversion Device SLEEP? ADIF = 0 No Finish Conversion SLEEP Power-down A ADIF = 1 Wait 2T AD 2000 Microchip Technology Inc. PIC17C7XX Yes Finish Conversion SLEEP Instruction ADIF = 1 No Yes Wake-up Finish Conversion From SLEEP ADIF = 1 No Stay in SLEEP Wait 2T ...
Page 188
... This forces the A/D module to be turned off, and any conversion is aborted. The value that is in the ADRESH:ADRESL registers is not modified for ADRESH:ADRESL registers will contain unknown data after a Power-on Reset. 10-Bit Result ADFM = RESULT ADRESH 10-bits Left Justified a Power-on Reset. The 0 0000 00 ADRESL 2000 Microchip Technology Inc. ...
Page 189
... AD minimized to reduce inaccuracies due to noise and sampling capacitor bleed off. 2000 Microchip Technology Inc. In systems where the device will enter SLEEP mode after the start of the A/D conversion, the RC clock source selection is required. In this mode, the digital noise from the modules in SLEEP are stopped ...
Page 190
... AN5 AN4 1111 1111 1111 1111 RG1/ RG0/ xxxx 0000 uuuu 0000 AN2 AN3 — ADON 0000 -0-0 0000 -0-0 PCFG0 000- 0000 000- 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 2000 Microchip Technology Inc. ...
Page 191
... RC oscillator oscillator Shaded bits (—) Reserved 2000 Microchip Technology Inc. The PIC17CXXX has a Watchdog Timer which can be shut-off only through EPROM bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on POR and BOR. One is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable ...
Page 192
... The user can program two configuration bits (FOSC1:FOSC0) to select one of these four modes: • LF Low Power Crystal • XT Crystal/Resonator • EC External Clock Input • RC Resistor/Capacitor For information on the different oscillator types and how to use them, please refer to Section 4.0. 2000 Microchip Technology Inc. ...
Page 193
... Shaded cells are not used by the WDT. Note 1: This value will be as the device was programmed unprogrammed, will read as all '1's. 2000 Microchip Technology Inc. 17.3.2 CLEARING THE WDT AND POSTSCALER The WDT and postscaler are cleared when: • ...
Page 194
... This needs to be taken into account OSC when considering the interrupt response time when coming out of SLEEP (2) T OST Processor in SLEEP PC+1 PC+2 Inst (PC+1) SLEEP (2) Interrupt Latency 0004h 0005h Inst (PC+2) Inst (PC+1) Dummy Cycle 2000 Microchip Technology Inc. ...
Page 195
... T0CKI input should The contributions DD SS from on-chip pull-ups on PORTB should also be con- sidered and disabled, when possible. 2000 Microchip Technology Inc. PIC17C7XX 17.5 Code Protection The code in the program memory can be protected by selecting the microcontroller in Code Protected mode (PM2:PM0 = ’000’). ...
Page 196
... TEST TEST MCLR/V MCLR DS30289B-page 196 For complete details of serial programming, please refer to the PIC17C7XX Programming Specification. (Contact your local Microchip Technology Sales Office for availability.) FIGURE 17-3: External Connector Signals + These IHH TEST CNTL pin. Also Dev. CLK Data I/O Data CLK ...
Page 197
... One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 25 MHz, the normal instruction execution time is 160 ns conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 320 ns. 2000 Microchip Technology Inc. PIC17C7XX TABLE 18-1: OPCODE FIELD DESCRIPTIONS ...
Page 198
... Q1 cycle. So, there is no issue on doing R-M-W instructions on registers which contain these bits 0 ALUSTA will clear register PCH PCLATH; PCL dest PCLATH PCH; 8-bit destination value PCL ALU operand PCLATH PCH; 8-bit result PCL 2000 Microchip Technology Inc. ...
Page 199
... Q cycles to the instruction cycle. FIGURE 18-2: Q CYCLE ACTIVITY OSC 2000 Microchip Technology Inc. The four Q cycles that make up an instruction cycle (T ) can be generalized as: CY Q1: Instruction Decode Cycle or forced No operation Q2: Instruction Read Cycle or No operation Q3: Process the Data ...
Page 200
... Microchip Technology Inc. Notes Z None 3 Z None 6,8 None 2,6,8 None 2,6 None 6,8 None ...