PIC17LC756A-08/L Microchip Technology, PIC17LC756A-08/L Datasheet - Page 33

• Manufacturer Part Number: PIC17LC756A-08/L
• Description: IC MCU OTP 16KX16 A/D 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17LC756A-08/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• Processor Series: PIC17LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 902 B
• Interface Type: I2C, MSSP, RS- 232, SCI, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 8
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 12 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

6.0
PIC17C7XX devices have 18 sources of interrupt:
• External interrupt from the RA0/INT pin
• Change on RB7:RB0 pins
• TMR0 Overflow
• TMR1 Overflow
• TMR2 Overflow
• TMR3 Overflow
• USART1 Transmit buffer empty
• USART1 Receive buffer full
• USART2 Transmit buffer empty
• USART2 Receive buffer full
• SSP Interrupt
• SSP I
• A/D conversion complete
• Capture1
• Capture2
• Capture3
• Capture4
• T0CKI edge occurred
There are six registers used in the control and status of
interrupts. These are:
• CPUSTA
• INTSTA
• PIE1
• PIR1
• PIE2
• PIR2
The CPUSTA register contains the GLINTD bit. This is
the Global Interrupt Disable bit. When this bit is set, all
interrupts are disabled. This bit is part of the controller
core functionality and is described in the Section 6.4.
FIGURE 6-1:
2000 Microchip Technology Inc.
2
INTERRUPTS
C bus collision interrupt
TMR1IF
TMR1IE
CA4IF
CA4IE
SSPIF
SSPIE
CA1IF
CA1IE
TX2IF
TX2IE
RBIF
RBIE
TMR3IF
TMR3IE
CA2IF
CA2IE
RC2IF
RC2IE
BCLIF
BCLIE
CA3IF
CA3IE
TX1IF
TX1IE
INTERRUPT LOGIC
TMR2IF
TMR2IE
RC1IF
RC1IE
ADIF
ADIE
T0CKIF
T0CKIE
INTF
INTE
PEIF
PEIE
T0IF
T0IE
When an interrupt is responded to, the GLINTD bit is
automatically set to disable any further interrupts, the
return address is pushed onto the stack and the PC is
loaded with the interrupt vector address. There are four
interrupt vectors. Each vector address is for a specific
interrupt source (except the peripheral interrupts, which
all vector to the same address). These sources are:
• External interrupt from the RA0/INT pin
• TMR0 Overflow
• T0CKI edge occurred
• Any peripheral interrupt
When program execution vectors to one of these inter-
rupt vector addresses (except for the peripheral inter-
rupts), the interrupt flag bit is automatically cleared.
Vectoring to the peripheral interrupt vector address
does not automatically clear the source of the interrupt.
In the peripheral Interrupt Service Routine, the
source(s) of the interrupt can be determined by testing
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid infinite interrupt requests.
When an interrupt condition is met, that individual inter-
rupt flag bit will be set, regardless of the status of its
corresponding mask bit or the GLINTD bit.
For external interrupt events, there will be an interrupt
latency. For two-cycle instructions, the latency could be
one instruction cycle longer.
The “return from interrupt” instruction, RETFIE, can be
used to mark the end of the Interrupt Service Routine.
When this instruction is executed, the stack is “POPed”
and the GLINTD bit is cleared (to re-enable interrupts).
INTSTA
GLINTD (CPUSTA<4>)
PIC17C7XX
Wake-up (If in SLEEP mode)
or terminate long write
DS30289B-page 33
Interrupt to CPU