PIC17LC756A-08/L Microchip Technology, PIC17LC756A-08/L Datasheet - Page 118

• Manufacturer Part Number: PIC17LC756A-08/L
• Description: IC MCU OTP 16KX16 A/D 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17LC756A-08/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• Processor Series: PIC17LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 902 B
• Interface Type: I2C, MSSP, RS- 232, SCI, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 8
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 12 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC17C7XX
The USART can be configured as a full duplex asyn-
chronous system that can communicate with peripheral
devices such as CRT terminals and personal comput-
ers, or it can be configured as a half duplex synchro-
nous system that can communicate with peripheral
devices such as A/D or D/A integrated circuits, Serial
EEPROMs etc. The USART can be configured in the
following modes:
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
REGISTER 14-2: RCSTA1 REGISTER (ADDRESS: 13h, BANK 0)
DS30289B-page 118
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RCSTA2 REGISTER (ADDRESS: 13h, BANK 4)
bit 7
SPEN: Serial Port Enable bit
1 = Configures TX/CK and RX/DT pins as serial port pins
0 = Serial port disabled
RX9: 9-bit Receive Select bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
SREN: Single Receive Enable bit
This bit enables the reception of a single byte. After receiving the byte, this bit is automatically
cleared.
Synchronous mode:
1 = Enable reception
0 = Disable reception
Asynchronous mode:
Don’t care
CREN: Continuous Receive Enable bit
This bit enables the continuous reception of serial data.
Asynchronous mode:
1 = Enable continuous reception
0 = Disables continuous reception
Synchronous mode:
1 = Enables continuous reception until CREN is cleared (CREN overrides SREN)
0 = Disables continuous reception
Unimplemented: Read as '0'
FERR: Framing Error bit
1 = Framing error (updated by reading RCREG)
0 = No framing error
bit OERR: Overrun Error bit
1 = Overrun (cleared by clearing CREN)
0 = No overrun error
RX9D: 9th bit of Receive Data (can be the software calculated parity bit)
Legend:
R = Readable bit
- n = Value at POR Reset
R/W-0
SPEN
Note:
This bit is ignored in synchronous slave reception.
R/W-0
RX9
R/W-0
SREN
W = Writable bit
’1’ = Bit is set
R/W-0
CREN
The SPEN (RCSTA<7>) bit has to be set in order to
configure the I/O pins as the Serial Communication
Interface (USART).
The USART module will control the direction of the RX/
DT and TX/CK pins, depending on the states of the
USART configuration bits in the RCSTA and TXSTA
registers. The bits that control I/O direction are:
• SPEN
• TXEN
• SREN
• CREN
• CSRC
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
U-0
—
FERR
R-0
2000 Microchip Technology Inc.
x = Bit is unknown
OERR
R-0
RX9D
R-x
bit 0