PIC17LC756A-08/L Microchip Technology, PIC17LC756A-08/L Datasheet - Page 186

• Manufacturer Part Number: PIC17LC756A-08/L
• Description: IC MCU OTP 16KX16 A/D 68PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17LC756A-08/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-PLCC
• Processor Series: PIC17LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 902 B
• Interface Type: I2C, MSSP, RS- 232, SCI, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 8
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 12 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC17C7XX
16.3
The ADCON1, and DDR registers control the operation
of the A/D port pins. The port pins that are desired as
analog inputs must have their corresponding DDR bits
set (input). If the DDR bit is cleared (output), the digital
output level (V
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the DDR bits.
EXAMPLE 16-2:
FIGURE 16-4:
DS30289B-page 186
;
;
;
;
Note 1: When reading the port register, any pin
Ensure that the required sampling time for the selected input channel has elapsed.
Then the conversion may be started.
MOVLB
CLRF
MOVLW
MOVWF
MOVLB
BCF
BSF
BSF
BCF
MOVLB
BSF
Configuring Analog Port Pins
:
:
2: Analog levels on any pin that is defined as
T
configured as an analog input channel will
read as cleared (a low level). Pins config-
ured as digital inputs, will convert an ana-
log input. Analog levels on a digitally
configured input will not affect the conver-
sion accuracy.
a digital input (including the AN15:AN0
pins), may cause the input buffer to con-
sume current that is out of the devices
specification.
CY
Set GO bit
OH
Holding capacitor is disconnected from analog input (typically 100 ns).
to T
5
ADCON1, F
0x01
ADCON0
4
PIR2, ADIF
PIE2, ADIE
INTSTA, PEIE
CPUSTA, GLINTD
5
ADCON0, GO
or V
AD
OL
Conversion starts.
A/D CONVERSION
A/D CONVERSION T
T
) will be converted.
AD
1 T
AD
b9
2 T
AD
b8
; Bank 5
; Configure A/D inputs, All analog, TAD = Fosc/8, left just.
; A/D is on, Channel 0 is selected
;
; Bank 4
; Clear A/D interrupt flag bit
; Enable A/D interrupts
; Enable peripheral interrupts
; Enable all interrupts
; Bank 5
; Start A/D Conversion
;
;
3 T
The ADIF bit will be set and the GO/DONE bit
is cleared upon completion of the A/D Conversion
AD
b7
Next Q4: ADRES is loaded,
AD
4 T
CYCLES
AD
b6
5 T
GO bit is cleared,
ADIF bit is set,
holding capacitor is connected to analog input.
AD
b5
6 T
16.4
Example 16-2 shows how to perform an A/D conver-
sion. The PORTF and lower four PORTG pins are con-
figured as analog inputs. The analog references
(V
A/D interrupt is enabled, and the A/D conversion clock
is F
pin (channel 0).
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D result register
pair will NOT be updated with the partially completed A/
D conversion sample. That is, the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers). After the A/D conversion
is aborted, a 2T
acquisition is started. After this 2T
on the selected channel is automatically started.
In Figure 16-4, after the GO bit is set, the first time seg-
ment has a minimum of T
AD
b4
REF
Note:
RC
7 T
+ and V
. The conversion is performed on the RG3/AN0
AD
b3
A/D Conversions
8 T
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
REF
AD
b2
-) are the device AV
AD
9
T
wait is required before the next
AD
b1
10 T
CY
2000 Microchip Technology Inc.
AD
b0
and a maximum of T
11
AD
DD
wait, acquisition
and AV
SS
AD
. The
.