AT91SAM7X256B-AU Atmel, AT91SAM7X256B-AU Datasheet - Page 111
![IC MCU 256KB FLASH 100LQFP](/photos/6/76/67646/313-100-lqfp_sml.jpg)
AT91SAM7X256B-AU
Manufacturer Part Number
AT91SAM7X256B-AU
Description
IC MCU 256KB FLASH 100LQFP
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7X256B-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Package
100LQFP
Device Core
ARM7TDMI
Family Name
91S
Maximum Speed
55 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
62
Interface Type
CAN/Ethernet/SPI/I2S/TWI/USART/USB
On-chip Adc
8-chx10-bit
Number Of Timers
3
Controller Family/series
AT91SAM7xxxxx
No. Of I/o's
62
Ram Memory Size
64KB
Cpu Speed
55MHz
No. Of Timers
1
Rohs Compliant
Yes
Cpu Family
91S
Device Core Size
32b
Frequency (max)
55MHz
Total Internal Ram Size
64KB
# I/os (max)
62
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
1.95/3.6V
Operating Supply Voltage (min)
1.65/3V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7X256B-AU
Manufacturer:
Atmel
Quantity:
1 800
Part Number:
AT91SAM7X256B-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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19.2.4.4
19.2.4.5
6120H–ATARM–17-Feb-09
General-purpose NVM Bits
Security Bit
General-purpose NVM bits do not interfere with the embedded Flash memory plane. (Does not
apply to EFC1 on the AT91SAM7X512.) These general-purpose bits are dedicated to protect
other parts of the product. They can be set (activated) or cleared individually. Refer to the prod-
uct definition section for the general-purpose NVM bit action.
The activation sequence is:
Two errors can be detected in the MC_FSR register after a programming sequence:
It is possible to deactivate a general-purpose NVM bit set previously. The clear sequence is:
Two errors can be detected in the MC_FSR register after a programming sequence:
The Clear General-purpose Bit command programs the general-purpose NVM bit to 1; the corre-
sponding bit GPNVM0 to GPNVMx in MC_FSR reads 0. The Set General-purpose Bit command
programs the general-purpose NVM bit to 0; the corresponding bit GPNVMx in MC_FSR reads
1.
Note:
The goal of the security bit is to prevent external access to the internal bus system. (Does not
apply to EFC1 on the AT91SAM7X512.) JTAG, Fast Flash Programming and Flash Serial Test
Interface features are disabled. Once set, this bit can be reset only by an external hardware
ERASE request to the chip. Refer to the product definition section for the pin name that controls
the ERASE. In this case, the full memory plane is erased and all lock and general-purpose NVM
bits are cleared. The security bit in the MC_FSR is cleared only after these operations. The acti-
vation sequence is:
• Start the Set General Purpose Bit command (SGPB) by writing the Flash Command Register
• When the bit is set, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises.
• Programming Error: A bad keyword and/or an invalid command have been written in the
• If the general-purpose bit number is greater than the total number of general-purpose bits,
• Start the Clear General-purpose Bit command (CGPB) by writing the Flash Command
• When the clear completes, the bit FRDY in the Flash Programming Status Register
• Programming Error: a bad keyword and/or an invalid command have been written in the
• If the number of the general-purpose bit set in the PAGEN field is greater than the total
• Start the Set Security Bit command (SSB) by writing the Flash Command Register.
with the SEL command and the number of the general-purpose bit to be set in the PAGEN
field.
If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the
Memory Controller is activated.
MC_FCR register
then the command has no effect.
Register with CGPB and the number of the general-purpose bit to be cleared in the PAGEN
field.
(MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the
interrupt line of the Memory Controller is activated.
MC_FCR register
number of general-purpose bits, then the command has no effect.
Access to the Flash in read mode is permitted when a Set, Clear or Get General-purpose NVM Bit
command is performed.
AT91SAM7X512/256/128 Preliminary
111
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