AT91SAM7X256B-AU Atmel, AT91SAM7X256B-AU Datasheet - Page 444

IC MCU 256KB FLASH 100LQFP

AT91SAM7X256B-AU

Manufacturer Part Number
AT91SAM7X256B-AU
Description
IC MCU 256KB FLASH 100LQFP
Manufacturer
Atmel
Series
AT91SAMr

Specifications of AT91SAM7X256B-AU

Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Package
100LQFP
Device Core
ARM7TDMI
Family Name
91S
Maximum Speed
55 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
62
Interface Type
CAN/Ethernet/SPI/I2S/TWI/USART/USB
On-chip Adc
8-chx10-bit
Number Of Timers
3
Controller Family/series
AT91SAM7xxxxx
No. Of I/o's
62
Ram Memory Size
64KB
Cpu Speed
55MHz
No. Of Timers
1
Rohs Compliant
Yes
Cpu Family
91S
Device Core Size
32b
Frequency (max)
55MHz
Total Internal Ram Size
64KB
# I/os (max)
62
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
1.95/3.6V
Operating Supply Voltage (min)
1.65/3V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant

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33.6.11
Register Name:PWM_CPRD[0. X-1]
Access Type: Read-write
Only the first 16 bits (internal channel counter size) are significant.
• CPRD: Channel Period
If the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be
calculated:
If the waveform is center-aligned, then the output waveform period depends on the counter source clock and can be
calculated:
444
– By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
– By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
31
23
15
7
256, 512, or 1024). The resulting period formula will be:
256, 512, or 1024). The resulting period formula will be:
(
------------------------------- -
(
------------------------------------------ -
(
------------------------------------------ -
(
----------------------------------------------------- -
X
CRPD
2
2
AT91SAM7X512/256/128 Preliminary
×
×
PWM Channel Period Register
×
MCK
CPRD
X
CPRD
MCK
MCK
×
MCK
×
CPRD
DIVA
)
×
DIVA
30
22
14
)
)
6
or
)
(
---------------------------------------------- -
or
CRPD
(
----------------------------------------------------- -
2
MCK
×
×
CPRD
DIVAB
29
21
13
MCK
5
×
)
DIVB
)
28
20
12
4
CPRD
CPRD
CPRD
CPRD
27
19
11
3
26
18
10
2
25
17
9
1
6120H–ATARM–17-Feb-09
24
16
8
0

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