AT91SAM7X256B-AU Atmel, AT91SAM7X256B-AU Datasheet - Page 442

IC MCU 256KB FLASH 100LQFP

AT91SAM7X256B-AU

Manufacturer Part Number
AT91SAM7X256B-AU
Description
IC MCU 256KB FLASH 100LQFP
Manufacturer
Atmel
Series
AT91SAMr

Specifications of AT91SAM7X256B-AU

Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Package
100LQFP
Device Core
ARM7TDMI
Family Name
91S
Maximum Speed
55 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
62
Interface Type
CAN/Ethernet/SPI/I2S/TWI/USART/USB
On-chip Adc
8-chx10-bit
Number Of Timers
3
Controller Family/series
AT91SAM7xxxxx
No. Of I/o's
62
Ram Memory Size
64KB
Cpu Speed
55MHz
No. Of Timers
1
Rohs Compliant
Yes
Cpu Family
91S
Device Core Size
32b
Frequency (max)
55MHz
Total Internal Ram Size
64KB
# I/os (max)
62
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
1.95/3.6V
Operating Supply Voltage (min)
1.65/3V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant

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Manufacturer
Quantity
Price
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AT91SAM7X256B-AU
Manufacturer:
Atmel
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Atmel
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33.6.9
Register Name: PWM_CMR[0..X-1]
Access Type: Read-write
• CPRE: Channel Pre-scaler
• CALG: Channel Alignment
0 = The period is left aligned.
1 = The period is center aligned.
• CPOL: Channel Polarity
0 = The output waveform starts at a low level.
1 = The output waveform starts at a high level.
• CPD: Channel Update Period
0 = Writing to the PWM_CUPDx will modify the duty cycle at the next period start event.
1 = Writing to the PWM_CUPDx will modify the period at the next period start event.
442
0
0
0
0
0
0
0
0
1
1
1
1
1
31
23
15
7
AT91SAM7X512/256/128 Preliminary
PWM Channel Mode Register
0
0
0
0
1
1
1
1
0
0
0
0
1
30
22
14
6
CPRE
Other
0
0
1
1
0
0
1
1
0
0
1
1
0
29
21
13
5
0
1
0
1
0
1
0
1
0
1
0
1
0
28
20
12
4
MCK
MCK/2
MCK/4
MCK/8
MCK/16
MCK/32
MCK/64
MCK/128
MCK/256
MCK/512
MCK/1024
CLKA
CLKB
Reserved
27
19
11
3
Channel Pre-scaler
CPD
26
18
10
2
CPRE
CPOL
25
17
9
1
6120H–ATARM–17-Feb-09
CALG
24
16
8
0

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