AT91SAM7X256B-AU Atmel, AT91SAM7X256B-AU Datasheet - Page 531
![IC MCU 256KB FLASH 100LQFP](/photos/6/76/67646/313-100-lqfp_sml.jpg)
AT91SAM7X256B-AU
Manufacturer Part Number
AT91SAM7X256B-AU
Description
IC MCU 256KB FLASH 100LQFP
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7X256B-AU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Package
100LQFP
Device Core
ARM7TDMI
Family Name
91S
Maximum Speed
55 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
62
Interface Type
CAN/Ethernet/SPI/I2S/TWI/USART/USB
On-chip Adc
8-chx10-bit
Number Of Timers
3
Controller Family/series
AT91SAM7xxxxx
No. Of I/o's
62
Ram Memory Size
64KB
Cpu Speed
55MHz
No. Of Timers
1
Rohs Compliant
Yes
Cpu Family
91S
Device Core Size
32b
Frequency (max)
55MHz
Total Internal Ram Size
64KB
# I/os (max)
62
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
1.95/3.6V
Operating Supply Voltage (min)
1.65/3V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM7X256B-AU
Manufacturer:
Atmel
Quantity:
1 800
Part Number:
AT91SAM7X256B-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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36.7.4.2
Figure 36-20. Time Triggered Principle
36.7.4.3
36.7.4.4
36.7.4.5
6120H–ATARM–17-Feb-09
Reference
Message
Time Triggered Mode
Synchronization by a Reference Message
Transmitting within a Time Window
Freezing the Internal Timer Counter
In Time Triggered Mode, basic cycles can be split into several time windows. A basic cycle starts
with a reference message. Each time a window is defined from the reference message, a trans-
mit operation should occur within a pre-defined time window. A mailbox must not win the
arbitration in a previous time window, and it must not be retried if the arbitration is lost in the time
window.
Time Trigger Mode is enabled by setting the TTM field in the CAN_MR register. In Time Trig-
gered Mode, as in Timestamp Mode, the CAN_TIMESTP field captures the values of the internal
counter, but the MTIMESTAMP fields in the CAN_MSRx registers are not active and are read at
0.
In Time Triggered Mode, the internal timer counter is automatically reset when a new message
is received in the last mailbox. This reset occurs after the reception of the End Of Frame on the
rising edge of the MRDY signal in the CAN_MSRx register. This allows synchronization of the
internal timer counter with the reception of a reference message and the start a new time
window.
A time mark is defined for each mailbox. It is defined in the 16-bit MTIMEMARK field of the
CAN_MMRx register. At each internal timer clock cycle, the value of the CAN_TIM is compared
with each mailbox time mark. When the internal timer counter reaches the MTIMEMARK value,
an internal timer event for the mailbox is generated for the mailbox.
In Time Triggered Mode, transmit operations are delayed until the internal timer event for the
mailbox. The application prepares a message to be sent by setting the MTCR in the CAN_MCRx
register. The message is not sent until the CAN_TIM value is less than the MTIMEMARK value
defined in the CAN_MMRx register.
If the transmit operation is failed, i.e., the message loses the bus arbitration and the next trans-
mit attempt is delayed until the next internal time trigger event. This prevents overlapping the
next time window, but the message is still pending and is retried in the next time window when
CAN_TIM value equals the MTIMEMARK value. It is also possible to prevent a retry by setting
the DRPT field in the CAN_MR register.
The internal counter can be frozen by setting TIMFRZ in the CAN_MR register. This prevents an
unexpected roll-over when the counter reaches FFFFh. When this occurs, it automatically
freezes until a new reset is issued, either due to a message received in the last mailbox or any
other reset counter operations. The TOVF bit in the CAN_SR register is set when the counter is
Time Cycle
Time Windows for Messages
AT91SAM7X512/256/128 Preliminary
Global Time
Reference
Message
531
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