AT91SAM7X256B-AU Atmel, AT91SAM7X256B-AU Datasheet - Page 239

• Manufacturer Part Number: AT91SAM7X256B-AU
• Description: IC MCU 256KB FLASH 100LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7X256B-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Device Core: ARM7TDMI
• Family Name: 91S
• Maximum Speed: 55 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 62
• Interface Type: CAN/Ethernet/SPI/I2S/TWI/USART/USB
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Controller Family/series: AT91SAM7xxxxx
• No. Of I/o's: 62
• Ram Memory Size: 64KB
• Cpu Speed: 55MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Cpu Family: 91S
• Device Core Size: 32b
• Frequency (max): 55MHz
• Total Internal Ram Size: 64KB
• # I/os (max): 62
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.65/3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Table 27-2.
Notes:
6120H–ATARM–17-Feb-09
Offset
0x0070
0x0074
0x0078
0x007C
to
0x009C
0x00A0
0x00A4
0x00A8
0x00AC
1. Reset value of PIO_PSR depends on the product implementation.
2. PIO_ODSR is Read-only or Read-write depending on PIO_OWSR I/O lines.
3. Reset value of PIO_PDSR depends on the level of the I/O lines. Reading the I/O line levels requires the clock of the PIO
4. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have
5. Only this set of registers clears the status by writing 1 in the first register and sets the status by writing 1 in the second
Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.
occurred.
register.
Register Mapping (Continued)
Register
Peripheral A Select Register
Peripheral B Select Register
AB Status Register
Reserved
Output Write Enable
Output Write Disable
Output Write Status Register
Reserved
(5)
(5)
(5)
AT91SAM7X512/256/128 Preliminary
Name
PIO_ASR
PIO_BSR
PIO_ABSR
PIO_OWER
PIO_OWDR
PIO_OWSR
Write-only
Write-only
Read-only
Write-only
Write-only
Read-only
Access
0x00000000
0x00000000
Reset
–
–
–
–
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