AT91SAM7X256B-AU Atmel, AT91SAM7X256B-AU Datasheet - Page 492

IC MCU 256KB FLASH 100LQFP

AT91SAM7X256B-AU

Manufacturer Part Number
AT91SAM7X256B-AU
Description
IC MCU 256KB FLASH 100LQFP
Manufacturer
Atmel
Series
AT91SAMr

Specifications of AT91SAM7X256B-AU

Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Package
100LQFP
Device Core
ARM7TDMI
Family Name
91S
Maximum Speed
55 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
62
Interface Type
CAN/Ethernet/SPI/I2S/TWI/USART/USB
On-chip Adc
8-chx10-bit
Number Of Timers
3
Controller Family/series
AT91SAM7xxxxx
No. Of I/o's
62
Ram Memory Size
64KB
Cpu Speed
55MHz
No. Of Timers
1
Rohs Compliant
Yes
Cpu Family
91S
Device Core Size
32b
Frequency (max)
55MHz
Total Internal Ram Size
64KB
# I/os (max)
62
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
1.95/3.6V
Operating Supply Voltage (min)
1.65/3V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant

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35.6
Table 35-2.
492
0x50 - 0xFC
Offset
0x0C
0x1C
0x2C
0x4C
0x00
0x04
0x08
0x10
0x14
0x18
0x20
0x24
0x28
0x30
0x34
Analog-to-Digital Converter (ADC) User Interface
...
AT91SAM7X512/256/128 Preliminary
Register Mapping
Register
Control Register
Mode Register
Reserved
Reserved
Channel Enable Register
Channel Disable Register
Channel Status Register
Status Register
Last Converted Data Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Channel Data Register 0
Channel Data Register 1
...
Channel Data Register 7
Reserved
ADC_CHER
ADC_CHDR
ADC_CHSR
ADC_LCDR
ADC_CDR0
ADC_CDR1
ADC_CDR7
ADC_IMR
ADC_IDR
ADC_IER
ADC_CR
ADC_MR
ADC_SR
Name
...
Read-write
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Write-only
Write-only
Write-only
Write-only
Write-only
Access
...
6120H–ATARM–17-Feb-09
0x000C0000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Reset
...

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