MC9S12XA256CAL Freescale Semiconductor, MC9S12XA256CAL Datasheet - Page 1022

• Manufacturer Part Number: MC9S12XA256CAL
• Description: IC MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA256CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• No. Of Timers: 1
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XA
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 16 Channel)
• Package: 112LQFP
• Family Name: HCS12
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
24.0.5.57 Port J Interrupt Flag Register (PIFJ)
Read: Anytime.
Write: Anytime.
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based
on the state of the PPSJ register. To clear this flag, write logic level “1” to the corresponding bit in the PIFJ
register. Writing a “0” has no effect.
24.0.5.58 Port AD1 Data Register 0 (PT0AD1)
Read: Anytime.
Write: Anytime.
This register is associated with AD1 pins PAD[15:8]. These pins can also be used as general purpose I/O.
1024
PIEJ[7:6]
PIEJ[1:0]
PIFJ[7:6]
PIFJ[1:0]
Reset
Reset
Field
Field
7–0
7–0
W
W
R
R
PT0AD115
PIFJ7
Interrupt Enable Port J
0 Interrupt is disabled (interrupt flag masked).
1 Interrupt is enabled.
Interrupt Flags Port J
0 No active edge pending. Writing a “0” has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0
0
7
7
Writing a logic level “1” clears the associated flag.
= Unimplemented or Reserved
PT0AD114
PIFJ6
0
0
6
6
Figure 24-59. Port J Interrupt Flag Register (PIFJ)
Figure 24-60. Port AD1 Data Register 0 (PT0AD1)
PT0AD113
Table 24-52. PIEJ Field Descriptions
Table 24-53. PIEJ Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
0
5
5
PT0AD112
0
0
0
4
4
Description
Description
PT0AD111
0
0
0
3
3
PT0AD110
0
0
0
2
2
PT0AD19
Freescale Semiconductor
PIFJ1
0
0
1
1
PT0AD18
PIFJ0
0
0
0
0