MC9S12XA256CAL Freescale Semiconductor, MC9S12XA256CAL Datasheet - Page 146

• Manufacturer Part Number: MC9S12XA256CAL
• Description: IC MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA256CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• No. Of Timers: 1
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XA
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 16 Channel)
• Package: 112LQFP
• Family Name: HCS12
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description
4.3.2.10
This read-only register contains the Conversion Complete Flags CCF15 to CCF8.
Read: Anytime
Write: Anytime, no effect
146
CCF[15:8]
Reset
Field
7:0
W
R
SC
CCF15
1
1
1
1
1
1
ATD Status Register 2 (ATDSTAT2)
0
7
Conversion Complete Flag Bits — A conversion complete flag is set at the end of each conversion in a
conversion sequence. The flags are associated with the conversion position in a sequence (and also the result
register number). Therefore, CCF8 is set when the ninth conversion in a sequence is complete and the result
is available in result register ATDDR8; CCF9 is set when the tenth conversion in a sequence is complete and
the result is available in ATDDR9, and so forth. A flag CCFx (x = 15, 14, 13, 12, 11, 10, 9, 8) is cleared when
one of the following occurs:
In case of a concurrent set and clear on CCFx: The clearing by method A) will overwrite the set. The clearing
by methods B) or C) will be overwritten by the set.
0 Conversion number x not completed
1 Conversion number x has completed, result ready in ATDDRx
• Write to ATDCTL5 (a new conversion sequence is started)
• If AFFC = 0 and read of ATDSTAT2 followed by read of result register ATDDRx
• If AFFC = 1 and read of result register ATDDRx
= Unimplemented or Reserved
CCF14
CD
0
0
0
0
0
1
0
6
Figure 4-12. ATD Status Register 2 (ATDSTAT2)
Table 4-20. Special Channel Select Coding
Table 4-21. ATDSTAT2 Field Descriptions
CCF13
MC9S12XDP512 Data Sheet, Rev. 2.21
CC
X
0
1
1
1
1
0
5
CCF12
CB
0
4
X
X
0
0
1
1
Description
CCF11
0
3
CA
X
X
0
1
0
1
CCF10
0
2
Analog Input Channel
(V
Reserved
Reserved
Reserved
RH
Freescale Semiconductor
V
+V
V
CCF9
RH
RL
RL
0
1
) / 2
CCF8
0
0