MC9S12XA256CAL Freescale Semiconductor, MC9S12XA256CAL Datasheet - Page 56

• Manufacturer Part Number: MC9S12XA256CAL
• Description: IC MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA256CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• No. Of Timers: 1
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XA
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 16 Channel)
• Package: 112LQFP
• Family Name: HCS12
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 1 Device Overview MC9S12XD-Family
1.2.3.3
This input only pin is reserved for test. This pin has a pulldown device.
1.2.3.4
This input only pin enables or disables the on-chip voltage regulator. The input has a pullup device.
1.2.3.5
Please ask your Freescale representative for the interactive application note to compute PLL loop filter
elements. Any current leakage on this pin must be avoided.
1.2.3.6
The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug communication. It
is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit
at the rising edge of RESET. The BKGD pin has a pullup device.
1.2.3.7
PAD[23:8] are general-purpose input or output pins and analog inputs AN[23:8] of the analog-to-digital
converter ATD1.
1.2.3.8
PAD[7:0] are general-purpose input or output pins and analog inputs AN[7:0] of the analog-to-digital
converter ATD0.
1.2.3.9
PAD[15:0] are general-purpose input or output pins and analog inputs AN[15:0] of the analog-to-digital
converter ATD1.
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TEST — Test Pin
VREGEN — Voltage Regulator Enable Pin
XFC — PLL Loop Filter Pin
BKGD / MODC — Background Debug and Mode Pin
PAD[23:8] / AN[23:8] — Port AD Input Pins of ATD1
PAD[7:0] / AN[7:0] — Port AD Input Pins of ATD0
PAD[15:0] / AN[15:0] — Port AD Input Pins of ATD1
The TEST pin must be tied to V
Figure 1-10. PLL Loop Filter Connections
MCU
MC9S12XDP512 Data Sheet, Rev. 2.21
XFC
SS
NOTE
V
in all applications.
DDPLL
R
C
0
S
V
DDPLL
C
P
Freescale Semiconductor