MC9S12XA256CAL Freescale Semiconductor, MC9S12XA256CAL Datasheet - Page 870

• Manufacturer Part Number: MC9S12XA256CAL
• Description: IC MCU 256K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA256CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 16KB
• Cpu Speed: 80MHz
• No. Of Timers: 1
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XA
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 16 Channel)
• Package: 112LQFP
• Family Name: HCS12
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.59 Port J Polarity Select Register (PPSJ)
Read: Anytime.
Write: Anytime.
This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting
a pull-up or pull-down device if enabled.
22.3.2.60 Port J Interrupt Enable Register (PIEJ)
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with
Port J.
872
PPSJ[7:4]
PPSJ[2:0]
PIEJ[7:4]
PIEJ[2:0]
Reset
Reset
Field
Field
7–0
7–0
W
W
R
R
PPSJ7
PIEJ7
Polarity Select Port J
0 Falling edge on the associated port J pin sets the associated flag bit in the PIFJ register.
1 Rising edge on the associated port J pin sets the associated flag bit in the PIFJ register.
Interrupt Enable Port J
0 Interrupt is disabled (interrupt flag masked).
1 Interrupt is enabled.
0
0
7
7
A pull-up device is connected to the associated port J pin, if enabled by the associated bit in register PERJ
and if the port is used as general purpose input or as IIC port.
A pull-down device is connected to the associated port J pin, if enabled by the associated bit in register PERJ
and if the port is used as input.
= Unimplemented or Reserved
= Unimplemented or Reserved
PPSJ6
PIEJ6
0
0
6
6
Figure 22-62. Port J Interrupt Enable Register (PIEJ)
Figure 22-61. Port J Polarity Select Register (PPSJ)
Table 22-55. PPSJ Field Descriptions
Table 22-56. PIEJ Field Descriptions
PPSJ5
MC9S12XDP512 Data Sheet, Rev. 2.21
PIEJ5
0
0
5
5
PPSJ4
PIEJ4
0
0
4
4
Description
Description
0
0
0
0
3
3
PPSJ2
PIEJ2
0
0
2
2
Freescale Semiconductor
PPSJ1
PIEJ1
0
0
1
1
PPSJ0
PIEJ0
0
0
0
0