M30280FCHP#U5B Renesas Electronics America, M30280FCHP#U5B Datasheet - Page 169

• Manufacturer Part Number: M30280FCHP#U5B
• Description: IC M16C/28 MCU FLASH 128K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FCHP#U5B

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M
R
R
1
e
E
Table 13.3 Base Timer Associated Register Settings (Time Measurement Function, Waveform
Figure 13.11 Base Timer Block Diagram
. v
6
J
G1BCR0
G1BCR1
G1BT
G1DV
Set the following registers to set the RST1 bit to "1" (base timer reset by matching the base timer with the G1PO0 register)
G1POCR0
G1PO0
G1FS
G1FE
C
0
Register
2
9
2 /
0 .
B
8
0
0
0
G
4
J
Two-phase pulse input
7
a
o r
Matched with G1PO0 register
0 -
. n
u
2
p
3
BTS bit in G1BCR1 register
0
, 1
0
(
Matched with G1BTRR
BCK1 to BCK0
RST4
IT
RST2 to RST1
BTS
UD1 to UD0
-
-
MOD1 to MOD0
-
FSC0
IFE0
M
Generation Function, Communication Function)
2
1
0
Input "L" to INT1 pin
0
6
7
C
f
1
or f
2 /
Bit
page 147
, 8
2
M
10
11
1
BCK1 to BCK0
6
C
2 /
f o
Select a count source
Select base timer reset timing
Select the base timer overflow
Select base timer reset timing
Used to start the base timer
Select how to count
Read or write base timer value
Divide ratio of a count source
Set to "00
Set reset cycle
Set to "0" (waveform generating function)
Set to "1" (channel operation start)
8
3
) B
RST4
RST1
RST2
8
5
(n+1) divider
2
" (single-phase waveform output mode)
(Note 1)
NOTES:
IT, RST4, BCK1 to BCK0 : Bits in the G1BCR0 register
RST2 to RST1: Bits in the G1BCR1 register
1. Divider is reset when the BTS bit is set to "0".
Base timer reset
f
BT1
Base timer
Function
b14 b15
0
1
Overflow signal
IT
Base timer
overflow request
13. Timer S