M30280FCHP#U5B Renesas Electronics America, M30280FCHP#U5B Datasheet - Page 291

• Manufacturer Part Number: M30280FCHP#U5B
• Description: IC M16C/28 MCU FLASH 128K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FCHP#U5B

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
1
. v
J
( Do not set the combination other than the above)
6
Table 16.6 I
0
16.6.4 Bits 4,5 : SDA/SCL Logic Output Value Monitor Bits SDAM/SCLM
16.6.5 Bits 6,7 : I
C
16.6.6 Address Receive in STOP/WAIT Mode
2
9
I3CK4[S4D0]
0 .
2 /
B
The SDAM/SCLM bits can monitor the logic value of the SDA and SCL output signals from the I
interface circuit. The SDAM bit monitors the SDA output logic value. The SCLM bit monitors the SCL
output logic value. The SDAM and SCLM bits are read-only. When write, set them to “0”.
The ICK1 bit, ICK0 bit, the ICK4 to ICK2 bits in the S4D0 register, and the PCLK0 bit in the PCLKR
register can select the system clock (V
The I
and 1/8 f
When WAIT mode is entered after the CM02 bit in the CM0 register is set to "0" (do not stop the peripheral
function clock in wait mode), the I
ever, the I
because the I
0
0
8
0
4
G
J
7
a
2
o r
0 -
. n
C bus system clock V
0
0
0
0
0
0
1
u
2
3
p
0
IIC
, 1
2
0
(
2
C system clock select bits
. f
M
C bus interface circuit is not operated in STOP mode or in low power consumption mode,
2
0
IIC
1
2
0
6
C bus system clock V
7
C
ICK3[S4D0]
can be selected between f
2 /
page 269
, 8
2
C System Clock Select Bits ICK0, ICK1
M
0
0
0
0
1
1
0
1
6
C
IIC
f o
2 /
8
3
can be selected among 1/2 f
) B
8
ICK2[S4D0]
5
2
C bus interface circuit can receive address data in WAIT mode. How-
IIC
0
0
0
1
0
1
0
IIC
is not supplied.
) of the I
1
and f
ICK1[S3D0]
2
2
C bus interface circuit.
by the PCLK0 bit setting.
0
0
1
X
X
X
X
IIC
, 1/2.5 f
ICK0[S3D0]
16. MULTI-MASTER I
IIC
0
1
0
X
X
X
X
, 1/3 f
IIC
, 1/4 f
I
V
V
V
V
V
V
V
2
IIC
IIC
IIC
IIC
IIC
IIC
IIC
C system clock
IIC
2
C bus INTERFACE
, 1/5 f
= 1/2 f(X
= 1/4 f(X
= 1/8 f(X
= 1/2.5 f(X
= 1/3 f(X
= 1/5 f(X
= 1/6 f(X
IIC
, 1/6 f
IN
IN
IN
IN
IN
IN
2
C bus
)
)
)
IN
)
)
)
)
IIC