M30280FCHP#U5B Renesas Electronics America, M30280FCHP#U5B Datasheet - Page 278

• Manufacturer Part Number: M30280FCHP#U5B
• Description: IC M16C/28 MCU FLASH 128K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FCHP#U5B

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
M
e
E
1
. v
J
6
Figure 16.6 S3D0 Register
0
C
2
9
0 .
B
2 /
0
0
8
0
4
J
G
NOTES:
7
a
I
o r
0 -
. n
2
b7
1. The PED and PEC bits are enabled when the ES0 bit in the S1D0 register is set to "1"(I
2. When the PCLK0 bit in the PCLKR register is set to "0", f
C0 Control Register 1
u
2
3
0
to "1", f
p
b6
, 1
0
(
M
2
b5
0
1
0
IIC
b4
6
7
C
=f
b3
1
2 /
.
page 256
, 8
b2
M
b1
1
b0
6
C
f o
2 /
Bit Symbol
SDAM
8
SCLM
3
PED
PEC
ICK0
ICK1
SIM
WIT
) B
8
5
Symbol
S3D0
The Logic Value Monitor
Bit of S
I C bus System Clock
Selection Bits,
if ICK4 to ICK2 bits in the
S4D0 register is "000
The Interrupt Enable Bit for
STOP Condition Detection
S
Bit
The Logic Value Monitor
Bit of S
The Interrupt Enable Bit for
Data Receive Completion
S
Bit
2
DAi
CLi
(1)
(1)
/Port Function Switch
/Port Function Switch
CL
DA
Bit Name
Output
Output
IIC
=f
Address
02E6
2
. When the PCLK0 bit in the PCLKR register is set
2
"
16
0: S
1: Port output pin (enable ES0 = 1)
0: S
1: Port output pin (enable ES0 = 1)
b7 b6
0: Disable the I
1: Enable the I
0: Disable the I
1: Enable the I
When setting NACK
(ACK bit = 0), write "0"
0: S
1: S
0: S
1: S
0 0 :
0 1 :
1 0 :
1 1 : Reserved
detection
interrupt upon completion
of receiving data
interrupt upon completion of
receiving data
interrupt of STOP condition
interrupt of STOP condition
detection
16. MULTI-MASTER I
DA
CL
DA
DA
CL
CL
V
V
I/O pin (enable ES0 = 1)
V
I/O pin (enable ES0 = 1)
output logic value = 0
output logic value = 1
output logic value = 0
output logic value = 1
IIC
IIC
IIC
=1/2 f
=1/4f
=1/8 f
Function
After Reset
00110000
2
2
2
2
C bus interface
C bus interface
C bus interface
C bus interface
IIC
IIC
IIC
2
C bus interface enabled).
(2)
2
2
C bus INTERFACE
RW
RW
RW
RW
RW
RW
RW
RO
RO