M30280FCHP#U5B Renesas Electronics America, M30280FCHP#U5B Datasheet - Page 44

• Manufacturer Part Number: M30280FCHP#U5B
• Description: IC M16C/28 MCU FLASH 128K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FCHP#U5B

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M
R
R
2. Central Processing Unit (CPU)
2.1 Data Registers (R0, R1, R2 and R3)
2.2 Address Registers (A0 and A1)
e
E
1
. v
J
Figure 2.1 Central Processing Unit Register
6
0
Figure 2.1 shows the CPU registers. The register bank is comprised of 7 registers (R0, R1, R2, R3, A0, A1
and FB) out of 13 CPU registers. Two sets of register banks are provided.
The R0, R1, R2 and R3 registers are 16 bit registers for transfer and arithmetic/logic operations.
The R0 and R1 registers can be split into high-order bits(R0H, R1H) and low-order bits (R0L, R1L) to be
used seperately as 8-bit data registers. Conversely, R2 and R0 can be combined with R2 to be used as a
32-bit data register (R2R0). The same applies to R1 and R2.
The register A0 consists of 16 bits, and is used for address register indirect addressing and address register
relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the same as A0.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
C
2
9
0 .
2 /
B
0
0
8
0
4
G
J
7
a
o r
0 -
. n
b31
u
2
NOTES:
3
p
0
, 1
1. The register bank is comprised of these registers. Two sets of register banks are provided.
0
(
M
2
0
1
0
6
7
C
2 /
The upper 4 bits of INTB are INTBH and
the lower 16 bits of INTB are INTBL.
, 8
page 22
R2
R3
M
b15
1
6
C
b19
b19
f o
2 /
8
INTBH
3
) B
8
5
b15
b15
b15
b15
R0H(R0's high bits)
R1H(R1's high bits)
b8
b7
b
PC
INTBL
US P
FL G
IS P
SB
R2
R3
A0
A1
FB
b8 b7
R1L(R1's low bits)
R0L(R0's low bits)
b0
b0
b0
b0
b0
b0
Interrupt table register
Program counter
User stack pointer
Interrupt stack pointer
Static base register
Flag register
Data registers
Address registers
Frame base registers
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved space
Processor interrupt priority level
Reserved space
2. Central Processing Unit(CPU)
(1)
(1)
(1)