M30280FCHP#U5B Renesas Electronics America, M30280FCHP#U5B Datasheet - Page 305

• Manufacturer Part Number: M30280FCHP#U5B
• Description: IC M16C/28 MCU FLASH 128K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FCHP#U5B

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M
R
R
17.5 Pin Assignment Control Register (PACR)
17.6 Digital Debounce Function
1
e
E
6
. v
J
Figure 17.10 shows the PACR register. After reset, set bits PACR2 to PACR0 in the PACR register before
a signal is input or output to each pin. When bits PACR2 to PACR0 are not set, some pins do not function
as I/O ports.
Bits PACR2 to PACR0: control pins to be used
U1MAP bit: controls pin assignments for the UART1 function.
bit to 0 (P6
(P7
The PRC2 bit in the PRCR protects the PACR register. Set the PACR register after setting the PRC2 bit in
the PRCR register.
Two digital debounce function circuits are provided. Level is determined when level is held, after applying
either a falling edge or rising edge to the pin, longer than the programmed filter width time. This enables
noise reduction.
This function is assigned to INT5/INPC17 and NMI/SD. Digital filter width is set in the NDDR register and
the P17DDR register respectively. Figure 17.11 shows the NDDR register and the P17DDR register.
Additionally, a digital debounce function is disabled to the port P1
Filter width : (n+1) x 1/f8
The NDDR register and the P17DDR register decrement count value with f8 as the count source. The
NDDR register and the P17DDR register indicate count time. Count value is reloaded if a falling edge or a
rising edge is applied to the pin.
The NDDR register and the P17DDR register can be set 00
function. Setting to FF
C
0
2
9
Value after reset: 000
To select the 80-pin package, set the bits to 011
To select the 64-pin package, set the bits to 010
To assign the UART1 function to P6
To assign the function to P7
2 /
0 .
B
3
8
0
0
to P7
0
G
4
J
7
o r
a
0 -
. n
u
0
2
p
7
3
)
0
, 1
to P6
(
0
M
2
1
0
6
0
4
C
7
).
2 /
, 8
page 283
16
2
M
.
disables the digital filter. See Figure 17.12 for details.
1
6
________
C
2 /
0
n: count value set in the NDDR register and P17DDR register
f o
/CTS
8
3
) B
8
5
1
/RTS
4
/CTS
1
, P7
1
/RTS
_______ _____
1
/CLK
2
2
1
.
.
, P6
1
, P7
5
/CLK
2
/RxD
16
1
, P6
to FF
1
7
, and P7
6
input and the port P8
/RxD
16
when using the digital debounce
1
, and P6
3
/TxD
1
17. Programmable I/O Ports
, set the U1MAP bit to 1
7
/TxD
1
5
, set the U1MAP
input.