M30280FCHP#U5B Renesas Electronics America, M30280FCHP#U5B Datasheet - Page 264

• Manufacturer Part Number: M30280FCHP#U5B
• Description: IC M16C/28 MCU FLASH 128K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FCHP#U5B

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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NOTES:
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6
Table 15.12 Delayed Trigger Mode 1 Specifications
Function
A/D Conversion Start
Condition
A/D Conversion Stop
Condition
Interrupt Request
Generation Timing
Readout of A/D Conversion Result
Analog Input Pin
0
15.1.8 Delayed Trigger Mode 1
C
2
9
In delayed trigger mode 1, analog voltages applied to the selected pins are converted one-by-one to a
digital code. When the input of the AD
conversion is started. After completing the AN
until the second AD
The single sweep conversion of the pins after the AN
trigger mode 1 specifications. Figure 15.24 shows the operation example of delayed trigger mode 1.
Figures 15.25 and 15.26 show each flag operation in the ADSTAT0 register that corresponds to the
operation example. Figure 15.27 shows the ADCON0 to ADCON2 registers in delayed trigger mode 1.
Figure 15.28 shows the ADTRGCON register in delayed trigger mode 1. Table 15.13 shows the trigger
select bit setting in delayed trigger mode 1.
1. Do not generate the next AD
2. The AD
3. Do not write “1” (A/D conversion started) to the ADST bit in delayed trigger mode 1. When write
4. AN0
0 .
2 /
B
0
0
8
lected pins complete A/D conversion. When an AD
conversion, its trigger is ignored. The falling edge of AD
complete A/D conversion, is considered to be the next AN0 pin conversion start condition.
___________
AD
may not be detected. Do not generate the AD
“1”,unexpected interrupts may be generated.
need to belong to the same group.
0
4
G
J
Item
7
a
o r
TRG
0 -
. n
___________
0
u
2
to AN0
3
p
0
, 1
TRG
0
pin falling edge is generated in shorter periods than fAD, the second AD
(
M
2
0
1
pin falling edge is detected synchronized with the operation clock fAD. Therefore, when the
0
6
7
7
C
___________
and AN2
2 /
page 242
TRG
, 8
M
pin falling edge is generated. When the second AD
1
6
0
The SCAN1 to SCAN0 bits in the ADCON1 register and ADGSEL1 to ADGSEL0
bits in the ADCON2 register select pins. Analog voltages applied to the selected
pins are converted one-by-one to a digital code. At this time, the
falling edge starts AN
starts conversion of the pins after AN
AN
AN
Single sweep conversion completed
Select from AN
and AN
Readout one of the AN0 to AN7 registers that corresponds to the selected pins
The AD
C
The AD
to AN2
•When the second AD
•When the AD
•A/D conversion completed
•Set the ADST bit to "0" (A/D conversion halted)
conversion of pins after the AN
f o
2 /
0
1
the AN
falling edge. The conversion of AN
conversion is completed.
___________
8
pin conversion start condition
pin conversion start condition
___________
3
___________
) B
8
TRG
5
TRG
0
TRG
7
___________
0
to AN
can be used in the same way as AN
pin, input voltage of AN
pin falling edge after the AN1 pin conversion is started until all se-
pin input changes state from “H” to “L” (falling edge)
TRG
___________
pin input changes state from “H” to “L” (falling edge)
TRG
7
0
pin (falling edge) changes state from “H” to “L”, a single sweep
(8 pins)
to AN
pin falling edge is generated again during single sweep
___________
___________
0
0
pin conversion and the second
pin conversion, the AN
TRG
TRG
1
(2 pins), AN
___________
(4)
Specification
pin falling edge is generated during A/D conversion of
pin falling edge in shorter periods than fAD.
TRG
1
___________
pin is restarted. Table 15.12 shows the delayed
1
(2)
1
pin, the conversion is not affected
TRG
pin falling edge is generated again during A/D
pin is sampled or after at the time of AD
1
1
pin
and the rest of the sweep starts when AN
pin, which was input after all selected pins
0
to AN
1
3
pin is not sampled and converted
(4 pins), AN
0
to AN
TRG
___________
AD
(3)
TRG
falling edge is generated,
7
. However, all input pins
___________
pin falling edge
0
TRG
to AN
(1)
___________
AD
TRG
pin falling edge
15. A/D Converter
5
___________
(6 pins)
pin
TRG
0