M30280FCHP#U5B Renesas Electronics America, M30280FCHP#U5B Datasheet - Page 220

• Manufacturer Part Number: M30280FCHP#U5B
• Description: IC M16C/28 MCU FLASH 128K 80LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280FCHP#U5B

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M
R
R
1
e
E
6
Table 14.14 STSPSEL Bit Functions
Figure 14.25 STSPSEL Bit Functions
. v
J
Function
Output of SCL2 and SDA2 pins
C
0
Start/stop condition interrupt
request generation timing
2
9
2 /
0 .
B
14.1.3.3 Arbitration
8
0
0
Unmatching of the transmit data and SDA
edge of SCL
U2RB register is updated. If the ABC bit is set to "0" (updated bitwise), the ABT bit is set to “1” at the
same time unmatching is detected during check, and is cleared to “0” when not detected. In cases
when the ABC bit is set to “1”, if unmatching is detected even once during check, the ABT bit is set to
“1” (unmatching detected) at the falling edge of the clock pulse of 9th bit. If the ABT bit needs to be
updated bytewise, clear the ABT bit to “0” (undetected) after detecting acknowledge in the first byte,
before transferring the next byte.
Setting the ALS bit in the U2SMR2 register to “1” (SDA
occur, in which case the SDA
is set to “1” (unmatching detected).
0
G
4
J
7
o r
a
0 -
. n
SDA2
SDA2
(1) In slave mode,
(2) In master mode,
STPSEL bit
SCL2
STPSEL bit
SCL2
u
2
p
3
0
CKDIR is set to "0" (internal clock), CKPH is set to "1"(clock delayed)
CKDIR is set to "1" (external clock)
, 1
0
(
M
2
1
0
6
0
2
7
C
Set STAREQ
to "1" (start)
. Use the ABC bit in the U2SMR register to select the timing at which the ABT bit in the
2 /
, 8
page 198
0
M
1
Start condition detection
interrupt
6
Set to "1" by
program
C
2 /
f o
8
3
) B
2
8
5
pin is placed in the high-impedance state at the same time the ABT bit
STSPSEL = 0
Output transfer clock and data/
Program with a port determines
how the start condition or stop
condition is output
Start/stop condition are detec-
ted
Start condition detection
interrupt
1st
Set to "0" by
program
2nd
1st
3rd
2nd
4th
2
pin input data is checked synchronously with the rising
3rd
5th
4th
6th 7th
5th
2
output stop enabled) causes arbitration-lost to
6th
Set STPREQ
to "1" (start)
8th
7th
Stop condition detection
interrupt
9th bit
8th
STSPSEL = 1
The STAREQ, RSTAREQ and
STPREQ bit determine how the
start condition or stop condition is
output
are completed
Start/stop condition generation
Set to "1" by
program
9th bit
Stop condition detection
interrupt
Set to "0" by
program
14. Serial I/O